The GICR_ISENABLER<n>E characteristics are:
Enables forwarding of the corresponding PPI to the CPU interfaces.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ISENABLER<n>E are RES0.
A copy of this register is provided for each Redistributor.
GICR_ISENABLER<n>E is a 32-bit register.
For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
Set_enable_bit<x> | Meaning |
---|---|
0b0 | If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. |
0b1 | If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1. |
The reset behavior of this field is:
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICR_ISENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0100 + (4 * n) | GICR_ISENABLER<n>E |
Accesses on this interface are RW.
04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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