TRCOSLSR, Trace OS Lock Status Register

The TRCOSLSR characteristics are:

Purpose

Returns the status of the Trace OS Lock.

Configuration

External register TRCOSLSR bits [31:0] are architecturally mapped to AArch64 System register TRCOSLSR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCOSLSR are RES0.

Attributes

TRCOSLSR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0OSLM[2:1]RES0OSLKOSLM[0]

Bits [31:5]

Reserved, RES0.

OSLM, bits [4:3, 0]

OS Lock model.

The value of this field is an IMPLEMENTATION DEFINED choice of:

OSLMMeaning
0b000

Trace OS Lock is not implemented.

0b010

Trace OS Lock is implemented.

0b100

Trace OS Lock is not implemented, and the trace unit is controlled by the PE OS Lock.

All other values are reserved.

When FEAT_ETE is implemented, the values 0b000, 0b010 are not permitted

The OSLM field is split as follows:

Access to this field is RO.

Bit [2]

Reserved, RES0.

OSLK, bit [1]

OS Lock status.

OSLKMeaning
0b0

The OS Lock is unlocked.

0b1

The OS Lock is locked.

Note that this field indicates the state of the PE OS Lock.

Accessing TRCOSLSR

External debugger accesses to this register are unaffected by the OS Lock.

TRCOSLSR can be accessed through the external debug interface:

ComponentOffsetInstance
ETE0x304TRCOSLSR

This interface is accessible as follows:


04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.