The TRCPIDR1 characteristics are:
Provides discovery information about the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCPIDR1 are RES0.
TRCPIDR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | DES_0 | PART_1 |
Reserved, RES0.
Designer, JEP106 identification code, bits [3:0]. TRCPIDR1.DES_0 and TRCPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
For a component designed by Arm Limited, the JEP106 identification code is 0x3B.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, bits [11:8].
The part number is selected by the designer of the component, and is stored in TRCPIDR1.PART_1 and TRCPIDR0.PART_0.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFE4 | TRCPIDR1 |
This interface is accessible as follows:
04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.