TRCRSR, Resources Status Register

The TRCRSR characteristics are:

Purpose

Use this to set, or read, the status of the resources.

Configuration

External register TRCRSR bits [31:0] are architecturally mapped to AArch64 System register TRCRSR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCRSR are RES0.

Attributes

TRCRSR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0TAEVENT[3]EVENT[2]EVENT[1]EVENT[0]RES0EXTIN[3]EXTIN[2]EXTIN[1]EXTIN[0]

Bits [31:13]

Reserved, RES0.

TA, bit [12]

Tracing active.

TAMeaning
0b0

Tracing is not active.

0b1

Tracing is active.

The reset behavior of this field is:

EVENT[<m>], bit [m+8], for m = 3 to 0

Untraced status of ETEEvents.

EVENT[<m>]Meaning
0b0

An ETEEvent <m> has not occurred.

0b1

An ETEEvent <m> has occurred while the resources were in the Paused state.

This bit is RES0 if TRCIDR4.NUMRSPAIR == 0 || m > TRCIDR0.NUMEVENT.

The reset behavior of this field is:

Bits [7:4]

Reserved, RES0.

EXTIN[<m>], bit [m], for m = 3 to 0

The sticky status of the External Input Selectors.

EXTIN[<m>]Meaning
0b0

An event selected by External Input Selector <m> has not occurred.

0b1

At least one event selected by External Input Selector <m> has occurred while the resources were in the Paused state.

This bit is RES0 if m >= TRCIDR5.NUMEXTINSEL.

The reset behavior of this field is:

Accessing TRCRSR

Must always be programmed.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

TRCRSR can be accessed through the external debug interface:

ComponentOffsetInstance
ETE0x028TRCRSR

This interface is accessible as follows:


04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68

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