PMCGCR0, Counter Group Configuration Register 0

The PMCGCR0 characteristics are:

Purpose

Encodes the number of PMU.PMEVCNTR<n>_EL0 counters implemented.

Configuration

This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMCGCR0 are RES0.

PMCGCR0 is in the Core power domain.

Attributes

PMCGCR0 is a:

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0CG1NCCG0NC

Bits [63:16]

Reserved, RES0.

CG1NC, bits [15:8]

Number of counters in group 1, which comprises the instruction counter PMU.PMICNTR_EL0.

Reads as 0x01.

Access to this field is RO.

CG0NC, bits [7:0]

Number of counters in group 0, which comprises the event counters PMU.PMEVCNTR<n>_EL0 and the cycle counter PMU.PMCCNTR_EL0.

This field reads as PMU.PMCFGR.N.

Otherwise:

313029282726252423222120191817161514131211109876543210
RES0CG1NCCG0NC

Bits [31:16]

Reserved, RES0.

CG1NC, bits [15:8]

Number of counters in group 1, which comprises the instruction counter PMU.PMICNTR_EL0.

Reads as 0x01.

Access to this field is RO.

CG0NC, bits [7:0]

Number of counters in group 0, which comprises the event counters PMU.PMEVCNTR<n>_EL0 and the cycle counter PMU.PMCCNTR_EL0.

This field reads as PMU.PMCFGR.N.

Accessing PMCGCR0

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT32 is implemented
[31:0] Accessible at offset 0xCE0 from PMU

When FEAT_PMUv3_EXT64 is implemented
[63:0] Accessible at offset 0xCE0 from PMU


04/07/2023 11:24; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68

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