PMVIDSR

This register is present only when FEAT_PMUv3_EXT32 is implemented, FEAT_PCSRv8p2 is implemented and EL2 is implemented. Otherwise, direct accesses to PMVIDSR are RES0.

If FEAT_PMUv3_EXT64 is implemented, the same content is present in the same location, and can be accessed using PMVCIDSR[63:32].

Attributes

Field descriptions

Bits [31:16]

VMID[15:8], bits [15:8]
When FEAT_VMID16 is implemented:

Extension to VMID[7:0]. For more information, see VMID[7:0].

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

VMID, bits [7:0]

VMID sample. The VMID associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample was generated:

This field is set to an UNKNOWN value if any of the following apply:
- EL2 is disabled in the current Security state.
- The PE is executing at EL2.
- EL2 is enabled in the current Security state, the PE is executing at EL0, EL2 is using AArch64, HCR_EL2.E2H == 1, and HCR_EL2.TGE == 1.
Otherwise:
- If EL2 is using AArch64 and either FEAT_VMID16 is not implemented or VTCR_EL2.VS is 1, this field is set to VTTBR_EL2.VMID.
- If EL2 is using AArch64, FEAT_VMID16 is implemented, and VTCR_EL2.VS is 0, PMVIDSR.VMID[7:0] is set to VTTBR_EL2.VMID[7:0] and PMVIDSR.VMID[15:8] is RES0.
- If EL2 is using AArch32, this field is set to VTTBR.VMID.

Because the value written to PMVIDSR is an indirect read of the VMID value, it is CONSTRAINED UNPREDICTABLE whether PMVIDSR is set to the original or new value if PMU.PMPCSR samples:

An instruction that writes to the VMID value.
The next Context synchronization event.
Any instruction executed between these two instructions.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing PMVIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.

Accesses to this register use the following encodings:

Accessible at offset 0x20C from PMU

When DoubleLockStatus(), or !IsCorePowered() or OSLockStatus(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																VMID[15:8]								VMID

PMVIDSR, VMID Sample Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:16]

VMID[15:8], bits [15:8]
When FEAT_VMID16 is implemented:

Otherwise:

VMID, bits [7:0]

Accessing PMVIDSR

Accessible at offset 0x20C from PMU

PMVIDSR, VMID Sample Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:16]

VMID[15:8], bits [15:8]When FEAT_VMID16 is implemented:

Otherwise:

VMID, bits [7:0]

Accessing PMVIDSR

Accessible at offset 0x20C from PMU

VMID[15:8], bits [15:8]
When FEAT_VMID16 is implemented: