Lines Matching refs:src
29 #define src x1 macro
48 #define E_l src
104 add srcend, src, count
107 sub tmp1, dstin, src
134 add srcend, src, count
137 ldr A_q, [src], #16
139 and tmp1, src, 15
150 ldp B_q, C_q, [src]
167 ldr B_q, [src]
178 ldr A_l, [src]
188 ldr A_lw, [src]
200 ldrb A_lw, [src]
203 ldrb B_lw, [src, tmp1]
216 bic src, src, 15
217 ldp B_q, C_q, [src]
228 ldr D_q, [src, 32]
237 ldp D_q, G_q, [src, 32]
247 ldr F_q, [src, 64]
257 bic src, src, 15
258 ldp B_q, C_q, [src], #32
263 ldp D_q, E_q, [src], #32
278 prfm pldl1strm, [src, MEMCPY_PREFETCH_LDR]
279 ldp F_q, G_q, [src], #32
281 ldp H_q, I_q, [src], #32
282 prfm pldl1strm, [src, MEMCPY_PREFETCH_LDR]
283 ldp B_q, C_q, [src], #32
285 ldp D_q, E_q, [src], #32
294 ldp F_q, G_q, [src], #32
295 ldp H_q, I_q, [src], #32
300 ldp B_q, C_q, [src], #32
301 ldp D_q, E_q, [src], #32
360 ldp F_q, G_q, [src], #32
381 prfm pldl1strm, [src, MEMCPY_PREFETCH_LDR];\
382 ldp C_q, D_q, [src], #32;\
387 ldp F_q, G_q, [src], #32;\
416 add srcend, src, count
443 ldp E_q, F_q, [src, 32]
444 ldp G_q, H_q, [src]