Lines Matching refs:src
68 #define src r1 macro
230 vldr \vreg, [src, #\base]
232 vldr d0, [src, #\base + 8]
234 vldr d1, [src, #\base + 16]
236 vldr d2, [src, #\base + 24]
238 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
240 vldr d0, [src, #\base + 40]
242 vldr d1, [src, #\base + 48]
244 vldr d2, [src, #\base + 56]
249 vldr \vreg, [src, #\base]
251 vldr d0, [src, #\base + 8]
253 vldr d1, [src, #\base + 16]
255 vldr d2, [src, #\base + 24]
258 vldr d0, [src, #\base + 40]
260 vldr d1, [src, #\base + 48]
262 vldr d2, [src, #\base + 56]
290 neon_load_d0 src
296 ldrne tmp1, [src], #4
303 add src, src, tmp1
306 ldr tmp1, [src, #-(\i * 4)]
313 ldrhcs tmp1, [src], #2
314 ldrbne src, [src] /* Src is dead, use as a scratch. */
316 strbne src, [dst]
325 and tmp2, src, #7
344 ldrmi tmp1, [src], #4
347 ldrhcs tmp1, [src], #2
348 ldrbne tmp2, [src], #1
362 vldr d0, [src, #0]
364 vldr d1, [src, #8]
366 vldr d0, [src, #16]
368 vldr d1, [src, #24]
370 vldr d0, [src, #32]
372 vldr d1, [src, #40]
374 vldr d0, [src, #48]
376 vldr d1, [src, #56]
378 add src, src, #64
388 add src, src, tmp1
390 vldr d0, [src, #-(\i * 8)]
395 sub src, src, #8
398 ldrd A_l, A_h, [src, #8]
400 ldrd A_l, A_h, [src, #16]
402 ldrd A_l, A_h, [src, #24]
404 ldrd A_l, A_h, [src, #32]
406 ldrd A_l, A_h, [src, #40]
408 ldrd A_l, A_h, [src, #48]
410 ldrd A_l, A_h, [src, #56]
412 ldrd A_l, A_h, [src, #64]!
426 add src, src, #8
438 add src, src, tmp1
440 ldrd A_l, A_h, [src, #-(\i * 8)]
447 ldrne tmp1, [src], #4
450 ldrhcs tmp1, [src], #2
451 ldrbne tmp2, [src]
473 vldr d3, [src, #0]
474 vldr d4, [src, #64]
475 vldr d5, [src, #128]
476 vldr d6, [src, #192]
477 vldr d7, [src, #256]
479 vldr d0, [src, #8]
480 vldr d1, [src, #16]
481 vldr d2, [src, #24]
482 add src, src, #32
491 add src, src, #3 * 64
495 add src, src, #2 * 64
503 add src, src, #3 * 64
507 vldr d7, [src, #64]
509 vldr d0, [src, #64 + 8]
511 vldr d1, [src, #64 + 16]
513 vldr d2, [src, #64 + 24]
515 add src, src, #96
527 sub src, src, #8
529 pld [src, #8]
530 pld [src, #72]
532 pld [src, #136]
533 ldrd A_l, A_h, [src, #8]
537 ldrd B_l, B_h, [src, #16]
541 ldrd C_l, C_h, [src, #24]
545 pld [src, #200]
546 ldrd D_l, D_h, [src, #32]!
550 pld [src, #232]
552 ldrd A_l, A_h, [src, #40]
554 ldrd B_l, B_h, [src, #48]
556 ldrd C_l, C_h, [src, #56]
558 ldrd D_l, D_h, [src, #64]!
562 ldrd A_l, A_h, [src, #8]
564 ldrd B_l, B_h, [src, #16]
566 ldrd C_l, C_h, [src, #24]
568 ldrd D_l, D_h, [src, #32]
572 add src, src, #40
598 pld [src, #0]
599 pld [src, #64]
604 pld [src, #(2 * 64)]
608 ldrmi tmp1, [src], #4
611 ldrbne tmp1, [src], #1
612 ldrhcs tmp2, [src], #2
616 pld [src, #(3 * 64)]
620 pld [src, #(4 * 64)]
633 neon_load_multi d0-d3, src
634 neon_load_multi d4-d7, src
638 pld [src, #(4 * 64)]
640 neon_load_multi d0-d3, src
642 neon_load_multi d4-d7, src
651 sub src, src, #4
654 ldr A_l, [src, #4]
655 ldr A_h, [src, #8]
659 ldr B_l, [src, #12]
660 ldr B_h, [src, #16]
664 ldr C_l, [src, #20]
665 ldr C_h, [src, #24]
669 ldr D_l, [src, #28]
670 ldr D_h, [src, #32]!
674 pld [src, #(5 * 64) - (32 - 4)]
676 ldr A_l, [src, #36]
677 ldr A_h, [src, #40]
679 ldr B_l, [src, #44]
680 ldr B_h, [src, #48]
682 ldr C_l, [src, #52]
683 ldr C_h, [src, #56]
685 ldr D_l, [src, #60]
686 ldr D_h, [src, #64]!
690 ldr A_l, [src, #4]
691 ldr A_h, [src, #8]
693 ldr B_l, [src, #12]
694 ldr B_h, [src, #16]
696 ldr C_l, [src, #20]
697 ldr C_h, [src, #24]
699 ldr D_l, [src, #28]
700 ldr D_h, [src, #32]
705 add src, src, #36