| /sysdeps/mips/ |
| A D | lshift.S | 60 sw $8,0($4)
74 sw $8,12($4)
80 sw $8,8($4)
86 sw $8,4($4)
92 sw $8,0($4)
96 sw $8,-4($4)
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| A D | rshift.S | 57 sw $8,-4($4)
71 sw $8,-16($4)
77 sw $8,-12($4)
83 sw $8,-8($4)
89 sw $8,-4($4)
93 sw $8,0($4)
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| A D | add_n.S | 57 sw $11,0($4)
78 sw $11,0($4)
87 sw $13,4($4)
96 sw $11,8($4)
105 sw $13,12($4)
118 sw $11,0($4)
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| A D | sub_n.S | 57 sw $11,0($4)
78 sw $11,0($4)
87 sw $13,4($4)
96 sw $11,8($4)
105 sw $13,12($4)
118 sw $11,0($4)
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| A D | start.S | 145 sw $7, 24($sp) /* stack_end */
147 sw $0, 16($sp) /* Used to be fini. */
150 sw $2, 20($sp) /* rtld_fini */
154 sw $7, 24($sp) /* stack_end */
156 sw $0, 16($sp) /* Used to be fini. */
158 sw $2, 20($sp) /* rtld_fini */
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| A D | mul_1.S | 79 sw $10,0($4)
100 sw $10,0($4)
114 sw $10,0($4)
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| A D | addmul_1.S | 82 sw $3,0($4)
107 sw $3,0($4)
125 sw $3,0($4)
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| A D | submul_1.S | 82 sw $3,0($4)
107 sw $3,0($4)
125 sw $3,0($4)
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| /sysdeps/hppa/fpu/ |
| A D | feupdateenv.c | 25 union { unsigned long long l; unsigned int sw[2]; } s; in __feupdateenv() member
36 temp.__status_word |= s.sw[0] & (FE_ALL_EXCEPT << 27); in __feupdateenv()
41 temp.__status_word = s.sw[0] & (FE_ALL_EXCEPT << 27); in __feupdateenv()
45 temp.__status_word = (s.sw[0] & (FE_ALL_EXCEPT << 27)) | FE_ALL_EXCEPT; in __feupdateenv()
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| A D | fedisblxcpt.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in fedisableexcept() member
30 old_exc = s.sw[0] & FE_ALL_EXCEPT; in fedisableexcept()
32 s.sw[0] &= ~(excepts & FE_ALL_EXCEPT); in fedisableexcept()
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| A D | feenablxcpt.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in feenableexcept() member
30 old_exc = s.sw[0] & FE_ALL_EXCEPT; in feenableexcept()
32 s.sw[0] |= (excepts & FE_ALL_EXCEPT); in feenableexcept()
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| A D | fesetround.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in __fesetround() member
32 s.sw[0] &= ~FE_DOWNWARD; in __fesetround()
33 s.sw[0] |= round & FE_DOWNWARD; in __fesetround()
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| A D | fegetexcept.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in fegetexcept() member
31 return (s.sw[0] & FE_ALL_EXCEPT); in fegetexcept()
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| A D | ftestexcept.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in fetestexcept() member
31 return (s.sw[0] >> 27) & excepts & FE_ALL_EXCEPT; in fetestexcept()
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| A D | fgetexcptflg.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in fegetexceptflag() member
31 *flagp = (s.sw[0] >> 27) & excepts & FE_ALL_EXCEPT; in fegetexceptflag()
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| A D | fclrexcpt.c | 24 union { unsigned long long l; unsigned int sw[2]; } s; in feclearexcept() member
29 s.sw[0] &= ~((excepts & FE_ALL_EXCEPT) << 27); in feclearexcept()
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| /sysdeps/unix/sysv/linux/riscv/ |
| A D | sysdep.S | 39 sw a0, rtld_errno, t1
43 sw a0, 0(t1)
47 sw a0, %tprel_lo(errno)(t1)
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| A D | sysdep.h | 83 sw a0, rtld_errno, t1; \
91 sw a0, 0(t1); \
99 sw a0, %tprel_lo(errno)(t1); \
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| A D | getcontext.S | 58 sw a1, MCONTEXT_FSR(a0)
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| /sysdeps/mips/mips32/ |
| A D | crti.S | 76 sw $31,28($sp)
102 sw $31,28($sp)
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| /sysdeps/unix/mips/ |
| A D | sysdep.S | 62 sw t0, 0(v0)
90 sw v0, errno
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| /sysdeps/x86/fpu/ |
| A D | test-fenv-x87.c | 85 uint16_t sw = get_x87_sw (); in test_x87_sw_bits() local
86 printf ("Testing %s: sw = %x\n", test, sw); in test_x87_sw_bits()
87 if ((sw & mask) == bits) in test_x87_sw_bits()
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| /sysdeps/riscv/sys/ |
| A D | asm.h | 31 # define REG_S sw
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| /sysdeps/mips/sys/ |
| A D | asm.h | 313 # define REG_S sw
333 # define INT_S sw
362 # define LONG_S sw
404 # define PTR_S sw
433 # define PTR_S sw
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| /sysdeps/microblaze/ |
| A D | start.S | 58 sw r6,r1,r0
|