Lines Matching refs:DPLL
1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
54 - DPLL mode setting - defining any one or more of the following overrides
56 - ti,low-power-stop : DPLL supports low power stop mode, gating output
57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
58 - ti,lock : DPLL locks in programmed rate
59 - ti,min-div : the minimum divisor to start from to round the DPLL
61 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
63 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
65 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean