Lines Matching defs:exynos4_clock
12 struct exynos4_clock { struct
13 unsigned char res1[0x4200];
14 unsigned int src_leftbus;
15 unsigned char res2[0x1fc];
16 unsigned int mux_stat_leftbus;
17 unsigned char res4[0xfc];
18 unsigned int div_leftbus;
19 unsigned char res5[0xfc];
20 unsigned int div_stat_leftbus;
21 unsigned char res6[0x1fc];
22 unsigned int gate_ip_leftbus;
23 unsigned char res7[0x1fc];
24 unsigned int clkout_leftbus;
25 unsigned int clkout_leftbus_div_stat;
26 unsigned char res8[0x37f8];
27 unsigned int src_rightbus;
28 unsigned char res9[0x1fc];
29 unsigned int mux_stat_rightbus;
30 unsigned char res10[0xfc];
31 unsigned int div_rightbus;
32 unsigned char res11[0xfc];
33 unsigned int div_stat_rightbus;
34 unsigned char res12[0x1fc];
35 unsigned int gate_ip_rightbus;
36 unsigned char res13[0x1fc];
37 unsigned int clkout_rightbus;
38 unsigned int clkout_rightbus_div_stat;
39 unsigned char res14[0x3608];
40 unsigned int epll_lock;
41 unsigned char res15[0xc];
42 unsigned int vpll_lock;
43 unsigned char res16[0xec];
44 unsigned int epll_con0;
45 unsigned int epll_con1;
46 unsigned char res17[0x8];
47 unsigned int vpll_con0;
48 unsigned int vpll_con1;
49 unsigned char res18[0xe8];
50 unsigned int src_top0;
51 unsigned int src_top1;
52 unsigned char res19[0x8];
53 unsigned int src_cam;
54 unsigned int src_tv;
55 unsigned int src_mfc;
56 unsigned int src_g3d;
57 unsigned int src_image;
58 unsigned int src_lcd0;
59 unsigned int src_lcd1;
60 unsigned int src_maudio;
61 unsigned int src_fsys;
62 unsigned char res20[0xc];
63 unsigned int src_peril0;
64 unsigned int src_peril1;
65 unsigned char res21[0xb8];
66 unsigned int src_mask_top;
67 unsigned char res22[0xc];
68 unsigned int src_mask_cam;
69 unsigned int src_mask_tv;
70 unsigned char res23[0xc];
71 unsigned int src_mask_lcd0;
72 unsigned int src_mask_lcd1;
73 unsigned int src_mask_maudio;
74 unsigned int src_mask_fsys;
75 unsigned char res24[0xc];
76 unsigned int src_mask_peril0;
77 unsigned int src_mask_peril1;
78 unsigned char res25[0xb8];
79 unsigned int mux_stat_top;
80 unsigned char res26[0x14];
81 unsigned int mux_stat_mfc;
82 unsigned int mux_stat_g3d;
83 unsigned int mux_stat_image;
84 unsigned char res27[0xdc];
85 unsigned int div_top;
86 unsigned char res28[0xc];
87 unsigned int div_cam;
88 unsigned int div_tv;
89 unsigned int div_mfc;
90 unsigned int div_g3d;
91 unsigned int div_image;
92 unsigned int div_lcd0;
93 unsigned int div_lcd1;
94 unsigned int div_maudio;
95 unsigned int div_fsys0;
96 unsigned int div_fsys1;
97 unsigned int div_fsys2;
98 unsigned int div_fsys3;
99 unsigned int div_peril0;
100 unsigned int div_peril1;
101 unsigned int div_peril2;
102 unsigned int div_peril3;
103 unsigned int div_peril4;
104 unsigned int div_peril5;
105 unsigned char res29[0x18];
106 unsigned int div2_ratio;
107 unsigned char res30[0x8c];
108 unsigned int div_stat_top;
109 unsigned char res31[0xc];
110 unsigned int div_stat_cam;
111 unsigned int div_stat_tv;
112 unsigned int div_stat_mfc;
113 unsigned int div_stat_g3d;
114 unsigned int div_stat_image;
115 unsigned int div_stat_lcd0;
116 unsigned int div_stat_lcd1;
117 unsigned int div_stat_maudio;
118 unsigned int div_stat_fsys0;
119 unsigned int div_stat_fsys1;
120 unsigned int div_stat_fsys2;
121 unsigned int div_stat_fsys3;
122 unsigned int div_stat_peril0;
123 unsigned int div_stat_peril1;
124 unsigned int div_stat_peril2;
125 unsigned int div_stat_peril3;
126 unsigned int div_stat_peril4;
127 unsigned int div_stat_peril5;
128 unsigned char res32[0x18];
129 unsigned int div2_stat;
130 unsigned char res33[0x29c];
131 unsigned int gate_ip_cam;
132 unsigned int gate_ip_tv;
133 unsigned int gate_ip_mfc;
134 unsigned int gate_ip_g3d;
135 unsigned int gate_ip_image;
136 unsigned int gate_ip_lcd0;
137 unsigned int gate_ip_lcd1;
138 unsigned char res34[0x4];
139 unsigned int gate_ip_fsys;
140 unsigned char res35[0x8];
141 unsigned int gate_ip_gps;
142 unsigned int gate_ip_peril;
143 unsigned char res36[0xc];
144 unsigned int gate_ip_perir;
145 unsigned char res37[0xc];
146 unsigned int gate_block;
147 unsigned char res38[0x8c];
148 unsigned int clkout_cmu_top;
149 unsigned int clkout_cmu_top_div_stat;
150 unsigned char res39[0x37f8];
151 unsigned int src_dmc;
152 unsigned char res40[0xfc];
153 unsigned int src_mask_dmc;
154 unsigned char res41[0xfc];
155 unsigned int mux_stat_dmc;
156 unsigned char res42[0xfc];
157 unsigned int div_dmc0;
158 unsigned int div_dmc1;
159 unsigned char res43[0xf8];
160 unsigned int div_stat_dmc0;
161 unsigned int div_stat_dmc1;
162 unsigned char res44[0x2f8];
163 unsigned int gate_ip_dmc;
164 unsigned char res45[0xfc];
165 unsigned int clkout_cmu_dmc;
166 unsigned int clkout_cmu_dmc_div_stat;
167 unsigned char res46[0x5f8];
168 unsigned int dcgidx_map0;
169 unsigned int dcgidx_map1;
170 unsigned int dcgidx_map2;
171 unsigned char res47[0x14];
172 unsigned int dcgperf_map0;
173 unsigned int dcgperf_map1;
174 unsigned char res48[0x18];
175 unsigned int dvcidx_map;
176 unsigned char res49[0x1c];
177 unsigned int freq_cpu;
178 unsigned int freq_dpm;
179 unsigned char res50[0x18];
180 unsigned int dvsemclk_en;
181 unsigned int maxperf;
182 unsigned char res51[0x2f78];
183 unsigned int apll_lock;
184 unsigned char res52[0x4];
185 unsigned int mpll_lock;
186 unsigned char res53[0xf4];
187 unsigned int apll_con0;
188 unsigned int apll_con1;
189 unsigned int mpll_con0;
190 unsigned int mpll_con1;
191 unsigned char res54[0xf0];
192 unsigned int src_cpu;
193 unsigned char res55[0x1fc];
194 unsigned int mux_stat_cpu;
195 unsigned char res56[0xfc];
196 unsigned int div_cpu0;
197 unsigned int div_cpu1;
198 unsigned char res57[0xf8];
199 unsigned int div_stat_cpu0;
200 unsigned int div_stat_cpu1;
201 unsigned char res58[0x3f8];
202 unsigned int clkout_cmu_cpu;
203 unsigned int clkout_cmu_cpu_div_stat;
204 unsigned char res59[0x5f8];
205 unsigned int armclk_stopctrl;
206 unsigned int atclk_stopctrl;
207 unsigned char res60[0x8];
208 unsigned int parityfail_status;
209 unsigned int parityfail_clear;
210 unsigned char res61[0xe8];
211 unsigned int apll_con0_l8;
212 unsigned int apll_con0_l7;
213 unsigned int apll_con0_l6;
214 unsigned int apll_con0_l5;
215 unsigned int apll_con0_l4;
216 unsigned int apll_con0_l3;
217 unsigned int apll_con0_l2;
218 unsigned int apll_con0_l1;
219 unsigned int iem_control;
220 unsigned char res62[0xdc];
221 unsigned int apll_con1_l8;
222 unsigned int apll_con1_l7;
223 unsigned int apll_con1_l6;
224 unsigned int apll_con1_l5;
225 unsigned int apll_con1_l4;
226 unsigned int apll_con1_l3;
227 unsigned int apll_con1_l2;
228 unsigned int apll_con1_l1;
229 unsigned char res63[0xe0];
230 unsigned int div_iem_l8;
231 unsigned int div_iem_l7;
232 unsigned int div_iem_l6;
233 unsigned int div_iem_l5;
234 unsigned int div_iem_l4;
235 unsigned int div_iem_l3;
236 unsigned int div_iem_l2;
237 unsigned int div_iem_l1;