Lines Matching refs:offset
12 #define CVMX_BGXX_CMRX_CONFIG(offset, block_id) \ argument
13 (0x00011800E0000000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
14 #define CVMX_BGXX_CMRX_INT(offset, block_id) \ argument
15 (0x00011800E0000020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
16 #define CVMX_BGXX_CMRX_PRT_CBFC_CTL(offset, block_id) \ argument
17 (0x00011800E0000408ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
18 #define CVMX_BGXX_CMRX_RX_ADR_CTL(offset, block_id) \ argument
19 (0x00011800E00000A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
20 #define CVMX_BGXX_CMRX_RX_BP_DROP(offset, block_id) \ argument
21 (0x00011800E0000080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
22 #define CVMX_BGXX_CMRX_RX_BP_OFF(offset, block_id) \ argument
23 (0x00011800E0000090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
24 #define CVMX_BGXX_CMRX_RX_BP_ON(offset, block_id) \ argument
25 (0x00011800E0000088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
26 #define CVMX_BGXX_CMRX_RX_BP_STATUS(offset, block_id) \ argument
27 (0x00011800E00000A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
28 #define CVMX_BGXX_CMRX_RX_FIFO_LEN(offset, block_id) \ argument
29 (0x00011800E00000C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
30 #define CVMX_BGXX_CMRX_RX_ID_MAP(offset, block_id) \ argument
31 (0x00011800E0000028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
32 #define CVMX_BGXX_CMRX_RX_LOGL_XOFF(offset, block_id) \ argument
33 (0x00011800E00000B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
34 #define CVMX_BGXX_CMRX_RX_LOGL_XON(offset, block_id) \ argument
35 (0x00011800E00000B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
36 #define CVMX_BGXX_CMRX_RX_PAUSE_DROP_TIME(offset, block_id) \ argument
37 (0x00011800E0000030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
38 #define CVMX_BGXX_CMRX_RX_STAT0(offset, block_id) \ argument
39 (0x00011800E0000038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
40 #define CVMX_BGXX_CMRX_RX_STAT1(offset, block_id) \ argument
41 (0x00011800E0000040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
42 #define CVMX_BGXX_CMRX_RX_STAT2(offset, block_id) \ argument
43 (0x00011800E0000048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
44 #define CVMX_BGXX_CMRX_RX_STAT3(offset, block_id) \ argument
45 (0x00011800E0000050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
46 #define CVMX_BGXX_CMRX_RX_STAT4(offset, block_id) \ argument
47 (0x00011800E0000058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
48 #define CVMX_BGXX_CMRX_RX_STAT5(offset, block_id) \ argument
49 (0x00011800E0000060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
50 #define CVMX_BGXX_CMRX_RX_STAT6(offset, block_id) \ argument
51 (0x00011800E0000068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
52 #define CVMX_BGXX_CMRX_RX_STAT7(offset, block_id) \ argument
53 (0x00011800E0000070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
54 #define CVMX_BGXX_CMRX_RX_STAT8(offset, block_id) \ argument
55 (0x00011800E0000078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
56 #define CVMX_BGXX_CMRX_RX_WEIGHT(offset, block_id) \ argument
57 (0x00011800E0000098ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
58 #define CVMX_BGXX_CMRX_TX_CHANNEL(offset, block_id) \ argument
59 (0x00011800E0000400ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
60 #define CVMX_BGXX_CMRX_TX_FIFO_LEN(offset, block_id) \ argument
61 (0x00011800E0000418ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
62 #define CVMX_BGXX_CMRX_TX_HG2_STATUS(offset, block_id) \ argument
63 (0x00011800E0000410ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
64 #define CVMX_BGXX_CMRX_TX_OVR_BP(offset, block_id) \ argument
65 (0x00011800E0000420ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
66 #define CVMX_BGXX_CMRX_TX_STAT0(offset, block_id) \ argument
67 (0x00011800E0000508ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
68 #define CVMX_BGXX_CMRX_TX_STAT1(offset, block_id) \ argument
69 (0x00011800E0000510ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
70 #define CVMX_BGXX_CMRX_TX_STAT10(offset, block_id) \ argument
71 (0x00011800E0000558ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
72 #define CVMX_BGXX_CMRX_TX_STAT11(offset, block_id) \ argument
73 (0x00011800E0000560ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
74 #define CVMX_BGXX_CMRX_TX_STAT12(offset, block_id) \ argument
75 (0x00011800E0000568ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
76 #define CVMX_BGXX_CMRX_TX_STAT13(offset, block_id) \ argument
77 (0x00011800E0000570ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
78 #define CVMX_BGXX_CMRX_TX_STAT14(offset, block_id) \ argument
79 (0x00011800E0000578ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
80 #define CVMX_BGXX_CMRX_TX_STAT15(offset, block_id) \ argument
81 (0x00011800E0000580ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
82 #define CVMX_BGXX_CMRX_TX_STAT16(offset, block_id) \ argument
83 (0x00011800E0000588ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
84 #define CVMX_BGXX_CMRX_TX_STAT17(offset, block_id) \ argument
85 (0x00011800E0000590ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
86 #define CVMX_BGXX_CMRX_TX_STAT2(offset, block_id) \ argument
87 (0x00011800E0000518ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
88 #define CVMX_BGXX_CMRX_TX_STAT3(offset, block_id) \ argument
89 (0x00011800E0000520ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
90 #define CVMX_BGXX_CMRX_TX_STAT4(offset, block_id) \ argument
91 (0x00011800E0000528ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
92 #define CVMX_BGXX_CMRX_TX_STAT5(offset, block_id) \ argument
93 (0x00011800E0000530ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
94 #define CVMX_BGXX_CMRX_TX_STAT6(offset, block_id) \ argument
95 (0x00011800E0000538ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
96 #define CVMX_BGXX_CMRX_TX_STAT7(offset, block_id) \ argument
97 (0x00011800E0000540ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
98 #define CVMX_BGXX_CMRX_TX_STAT8(offset, block_id) \ argument
99 (0x00011800E0000548ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
100 #define CVMX_BGXX_CMRX_TX_STAT9(offset, block_id) \ argument
101 (0x00011800E0000550ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
102 #define CVMX_BGXX_CMR_BAD(offset) (0x00011800E0001020ull + ((offset) & 7) * 0x1000000ull) argument
103 #define CVMX_BGXX_CMR_BIST_STATUS(offset) (0x00011800E0000300ull + ((offset) & 7) * 0x1000000ull) argument
104 #define CVMX_BGXX_CMR_CHAN_MSK_AND(offset) (0x00011800E0000200ull + ((offset) & 7) * 0x1000000ull) argument
105 #define CVMX_BGXX_CMR_CHAN_MSK_OR(offset) (0x00011800E0000208ull + ((offset) & 7) * 0x1000000ull) argument
106 #define CVMX_BGXX_CMR_ECO(offset) (0x00011800E0001028ull + ((offset) & 7) * 0x1000000ull) argument
107 #define CVMX_BGXX_CMR_GLOBAL_CONFIG(offset) (0x00011800E0000008ull + ((offset) & 7) * 0x1000000ull) argument
108 #define CVMX_BGXX_CMR_MEM_CTRL(offset) (0x00011800E0000018ull + ((offset) & 7) * 0x1000000ull) argument
109 #define CVMX_BGXX_CMR_MEM_INT(offset) (0x00011800E0000010ull + ((offset) & 7) * 0x1000000ull) argument
110 #define CVMX_BGXX_CMR_NXC_ADR(offset) (0x00011800E0001018ull + ((offset) & 7) * 0x1000000ull) argument
111 #define CVMX_BGXX_CMR_RX_ADRX_CAM(offset, block_id) \ argument
112 (0x00011800E0000100ull + (((offset) & 31) + ((block_id) & 7) * 0x200000ull) * 8)
113 #define CVMX_BGXX_CMR_RX_LMACS(offset) (0x00011800E0000308ull + ((offset) & 7) * 0x1000000ull) argument
114 #define CVMX_BGXX_CMR_RX_OVR_BP(offset) (0x00011800E0000318ull + ((offset) & 7) * 0x1000000ull) argument
115 #define CVMX_BGXX_CMR_TX_LMACS(offset) (0x00011800E0001000ull + ((offset) & 7) * 0x1000000ull) argument
116 #define CVMX_BGXX_GMP_GMI_PRTX_CFG(offset, block_id) \ argument
117 (0x00011800E0038010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
118 #define CVMX_BGXX_GMP_GMI_RXX_DECISION(offset, block_id) \ argument
119 (0x00011800E0038040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
120 #define CVMX_BGXX_GMP_GMI_RXX_FRM_CHK(offset, block_id) \ argument
121 (0x00011800E0038020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
122 #define CVMX_BGXX_GMP_GMI_RXX_FRM_CTL(offset, block_id) \ argument
123 (0x00011800E0038018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
124 #define CVMX_BGXX_GMP_GMI_RXX_IFG(offset, block_id) \ argument
125 (0x00011800E0038058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
126 #define CVMX_BGXX_GMP_GMI_RXX_INT(offset, block_id) \ argument
127 (0x00011800E0038000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
128 #define CVMX_BGXX_GMP_GMI_RXX_JABBER(offset, block_id) \ argument
129 (0x00011800E0038038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
130 #define CVMX_BGXX_GMP_GMI_RXX_UDD_SKP(offset, block_id) \ argument
131 (0x00011800E0038048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
132 #define CVMX_BGXX_GMP_GMI_SMACX(offset, block_id) \ argument
133 (0x00011800E0038230ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
134 #define CVMX_BGXX_GMP_GMI_TXX_APPEND(offset, block_id) \ argument
135 (0x00011800E0038218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
136 #define CVMX_BGXX_GMP_GMI_TXX_BURST(offset, block_id) \ argument
137 (0x00011800E0038228ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
138 #define CVMX_BGXX_GMP_GMI_TXX_CTL(offset, block_id) \ argument
139 (0x00011800E0038270ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
140 #define CVMX_BGXX_GMP_GMI_TXX_INT(offset, block_id) \ argument
141 (0x00011800E0038500ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
142 #define CVMX_BGXX_GMP_GMI_TXX_MIN_PKT(offset, block_id) \ argument
143 (0x00011800E0038240ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
144 #define CVMX_BGXX_GMP_GMI_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ argument
145 (0x00011800E0038248ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
146 #define CVMX_BGXX_GMP_GMI_TXX_PAUSE_PKT_TIME(offset, block_id) \ argument
147 (0x00011800E0038238ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
148 #define CVMX_BGXX_GMP_GMI_TXX_PAUSE_TOGO(offset, block_id) \ argument
149 (0x00011800E0038258ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
150 #define CVMX_BGXX_GMP_GMI_TXX_PAUSE_ZERO(offset, block_id) \ argument
151 (0x00011800E0038260ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
152 #define CVMX_BGXX_GMP_GMI_TXX_SGMII_CTL(offset, block_id) \ argument
153 (0x00011800E0038300ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
154 #define CVMX_BGXX_GMP_GMI_TXX_SLOT(offset, block_id) \ argument
155 (0x00011800E0038220ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
156 #define CVMX_BGXX_GMP_GMI_TXX_SOFT_PAUSE(offset, block_id) \ argument
157 (0x00011800E0038250ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
158 #define CVMX_BGXX_GMP_GMI_TXX_THRESH(offset, block_id) \ argument
159 (0x00011800E0038210ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
160 #define CVMX_BGXX_GMP_GMI_TX_COL_ATTEMPT(offset) \ argument
161 (0x00011800E0039010ull + ((offset) & 7) * 0x1000000ull)
162 #define CVMX_BGXX_GMP_GMI_TX_IFG(offset) (0x00011800E0039000ull + ((offset) & 7) * 0x1000000ull) argument
163 #define CVMX_BGXX_GMP_GMI_TX_JAM(offset) (0x00011800E0039008ull + ((offset) & 7) * 0x1000000ull) argument
164 #define CVMX_BGXX_GMP_GMI_TX_LFSR(offset) (0x00011800E0039028ull + ((offset) & 7) * 0x1000000ull) argument
165 #define CVMX_BGXX_GMP_GMI_TX_PAUSE_PKT_DMAC(offset) \ argument
166 (0x00011800E0039018ull + ((offset) & 7) * 0x1000000ull)
167 #define CVMX_BGXX_GMP_GMI_TX_PAUSE_PKT_TYPE(offset) \ argument
168 (0x00011800E0039020ull + ((offset) & 7) * 0x1000000ull)
169 #define CVMX_BGXX_GMP_PCS_ANX_ADV(offset, block_id) \ argument
170 (0x00011800E0030010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
171 #define CVMX_BGXX_GMP_PCS_ANX_EXT_ST(offset, block_id) \ argument
172 (0x00011800E0030028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
173 #define CVMX_BGXX_GMP_PCS_ANX_LP_ABIL(offset, block_id) \ argument
174 (0x00011800E0030018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
175 #define CVMX_BGXX_GMP_PCS_ANX_RESULTS(offset, block_id) \ argument
176 (0x00011800E0030020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
177 #define CVMX_BGXX_GMP_PCS_INTX(offset, block_id) \ argument
178 (0x00011800E0030080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
179 #define CVMX_BGXX_GMP_PCS_LINKX_TIMER(offset, block_id) \ argument
180 (0x00011800E0030040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
181 #define CVMX_BGXX_GMP_PCS_MISCX_CTL(offset, block_id) \ argument
182 (0x00011800E0030078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
183 #define CVMX_BGXX_GMP_PCS_MRX_CONTROL(offset, block_id) \ argument
184 (0x00011800E0030000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
185 #define CVMX_BGXX_GMP_PCS_MRX_STATUS(offset, block_id) \ argument
186 (0x00011800E0030008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
187 #define CVMX_BGXX_GMP_PCS_RXX_STATES(offset, block_id) \ argument
188 (0x00011800E0030058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
189 #define CVMX_BGXX_GMP_PCS_RXX_SYNC(offset, block_id) \ argument
190 (0x00011800E0030050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
191 #define CVMX_BGXX_GMP_PCS_SGMX_AN_ADV(offset, block_id) \ argument
192 (0x00011800E0030068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
193 #define CVMX_BGXX_GMP_PCS_SGMX_LP_ADV(offset, block_id) \ argument
194 (0x00011800E0030070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
195 #define CVMX_BGXX_GMP_PCS_TXX_STATES(offset, block_id) \ argument
196 (0x00011800E0030060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
197 #define CVMX_BGXX_GMP_PCS_TX_RXX_POLARITY(offset, block_id) \ argument
198 (0x00011800E0030048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
199 #define CVMX_BGXX_SMUX_CBFC_CTL(offset, block_id) \ argument
200 (0x00011800E0020218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
201 #define CVMX_BGXX_SMUX_CTRL(offset, block_id) \ argument
202 (0x00011800E0020200ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
203 #define CVMX_BGXX_SMUX_EXT_LOOPBACK(offset, block_id) \ argument
204 (0x00011800E0020208ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
205 #define CVMX_BGXX_SMUX_HG2_CONTROL(offset, block_id) \ argument
206 (0x00011800E0020210ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
207 #define CVMX_BGXX_SMUX_RX_BAD_COL_HI(offset, block_id) \ argument
208 (0x00011800E0020040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
209 #define CVMX_BGXX_SMUX_RX_BAD_COL_LO(offset, block_id) \ argument
210 (0x00011800E0020038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
211 #define CVMX_BGXX_SMUX_RX_CTL(offset, block_id) \ argument
212 (0x00011800E0020030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
213 #define CVMX_BGXX_SMUX_RX_DECISION(offset, block_id) \ argument
214 (0x00011800E0020020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
215 #define CVMX_BGXX_SMUX_RX_FRM_CHK(offset, block_id) \ argument
216 (0x00011800E0020010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
217 #define CVMX_BGXX_SMUX_RX_FRM_CTL(offset, block_id) \ argument
218 (0x00011800E0020008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
219 #define CVMX_BGXX_SMUX_RX_INT(offset, block_id) \ argument
220 (0x00011800E0020000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
221 #define CVMX_BGXX_SMUX_RX_JABBER(offset, block_id) \ argument
222 (0x00011800E0020018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
223 #define CVMX_BGXX_SMUX_RX_UDD_SKP(offset, block_id) \ argument
224 (0x00011800E0020028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
225 #define CVMX_BGXX_SMUX_SMAC(offset, block_id) \ argument
226 (0x00011800E0020108ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
227 #define CVMX_BGXX_SMUX_TX_APPEND(offset, block_id) \ argument
228 (0x00011800E0020100ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
229 #define CVMX_BGXX_SMUX_TX_CTL(offset, block_id) \ argument
230 (0x00011800E0020160ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
231 #define CVMX_BGXX_SMUX_TX_IFG(offset, block_id) \ argument
232 (0x00011800E0020148ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
233 #define CVMX_BGXX_SMUX_TX_INT(offset, block_id) \ argument
234 (0x00011800E0020140ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
235 #define CVMX_BGXX_SMUX_TX_MIN_PKT(offset, block_id) \ argument
236 (0x00011800E0020118ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
237 #define CVMX_BGXX_SMUX_TX_PAUSE_PKT_DMAC(offset, block_id) \ argument
238 (0x00011800E0020150ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
239 #define CVMX_BGXX_SMUX_TX_PAUSE_PKT_INTERVAL(offset, block_id) \ argument
240 (0x00011800E0020120ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
241 #define CVMX_BGXX_SMUX_TX_PAUSE_PKT_TIME(offset, block_id) \ argument
242 (0x00011800E0020110ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
243 #define CVMX_BGXX_SMUX_TX_PAUSE_PKT_TYPE(offset, block_id) \ argument
244 (0x00011800E0020158ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
245 #define CVMX_BGXX_SMUX_TX_PAUSE_TOGO(offset, block_id) \ argument
246 (0x00011800E0020130ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
247 #define CVMX_BGXX_SMUX_TX_PAUSE_ZERO(offset, block_id) \ argument
248 (0x00011800E0020138ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
249 #define CVMX_BGXX_SMUX_TX_SOFT_PAUSE(offset, block_id) \ argument
250 (0x00011800E0020128ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
251 #define CVMX_BGXX_SMUX_TX_THRESH(offset, block_id) \ argument
252 (0x00011800E0020168ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
253 #define CVMX_BGXX_SPUX_AN_ADV(offset, block_id) \ argument
254 (0x00011800E00100D8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
255 #define CVMX_BGXX_SPUX_AN_BP_STATUS(offset, block_id) \ argument
256 (0x00011800E00100F8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
257 #define CVMX_BGXX_SPUX_AN_CONTROL(offset, block_id) \ argument
258 (0x00011800E00100C8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
259 #define CVMX_BGXX_SPUX_AN_LP_BASE(offset, block_id) \ argument
260 (0x00011800E00100E0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
261 #define CVMX_BGXX_SPUX_AN_LP_XNP(offset, block_id) \ argument
262 (0x00011800E00100F0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
263 #define CVMX_BGXX_SPUX_AN_STATUS(offset, block_id) \ argument
264 (0x00011800E00100D0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
265 #define CVMX_BGXX_SPUX_AN_XNP_TX(offset, block_id) \ argument
266 (0x00011800E00100E8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
267 #define CVMX_BGXX_SPUX_BR_ALGN_STATUS(offset, block_id) \ argument
268 (0x00011800E0010050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
269 #define CVMX_BGXX_SPUX_BR_BIP_ERR_CNT(offset, block_id) \ argument
270 (0x00011800E0010058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
271 #define CVMX_BGXX_SPUX_BR_LANE_MAP(offset, block_id) \ argument
272 (0x00011800E0010060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
273 #define CVMX_BGXX_SPUX_BR_PMD_CONTROL(offset, block_id) \ argument
274 (0x00011800E0010068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
275 #define CVMX_BGXX_SPUX_BR_PMD_LD_CUP(offset, block_id) \ argument
276 (0x00011800E0010088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
277 #define CVMX_BGXX_SPUX_BR_PMD_LD_REP(offset, block_id) \ argument
278 (0x00011800E0010090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
279 #define CVMX_BGXX_SPUX_BR_PMD_LP_CUP(offset, block_id) \ argument
280 (0x00011800E0010078ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
281 #define CVMX_BGXX_SPUX_BR_PMD_LP_REP(offset, block_id) \ argument
282 (0x00011800E0010080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
283 #define CVMX_BGXX_SPUX_BR_PMD_STATUS(offset, block_id) \ argument
284 (0x00011800E0010070ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
285 #define CVMX_BGXX_SPUX_BR_STATUS1(offset, block_id) \ argument
286 (0x00011800E0010030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
287 #define CVMX_BGXX_SPUX_BR_STATUS2(offset, block_id) \ argument
288 (0x00011800E0010038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
289 #define CVMX_BGXX_SPUX_BR_TP_CONTROL(offset, block_id) \ argument
290 (0x00011800E0010040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
291 #define CVMX_BGXX_SPUX_BR_TP_ERR_CNT(offset, block_id) \ argument
292 (0x00011800E0010048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
293 #define CVMX_BGXX_SPUX_BX_STATUS(offset, block_id) \ argument
294 (0x00011800E0010028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
295 #define CVMX_BGXX_SPUX_CONTROL1(offset, block_id) \ argument
296 (0x00011800E0010000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
297 #define CVMX_BGXX_SPUX_CONTROL2(offset, block_id) \ argument
298 (0x00011800E0010018ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
299 #define CVMX_BGXX_SPUX_FEC_ABIL(offset, block_id) \ argument
300 (0x00011800E0010098ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
301 #define CVMX_BGXX_SPUX_FEC_CONTROL(offset, block_id) \ argument
302 (0x00011800E00100A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
303 #define CVMX_BGXX_SPUX_FEC_CORR_BLKS01(offset, block_id) \ argument
304 (0x00011800E00100A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
305 #define CVMX_BGXX_SPUX_FEC_CORR_BLKS23(offset, block_id) \ argument
306 (0x00011800E00100B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
307 #define CVMX_BGXX_SPUX_FEC_UNCORR_BLKS01(offset, block_id) \ argument
308 (0x00011800E00100B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
309 #define CVMX_BGXX_SPUX_FEC_UNCORR_BLKS23(offset, block_id) \ argument
310 (0x00011800E00100C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
311 #define CVMX_BGXX_SPUX_INT(offset, block_id) \ argument
312 (0x00011800E0010220ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
313 #define CVMX_BGXX_SPUX_LPCS_STATES(offset, block_id) \ argument
314 (0x00011800E0010208ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
315 #define CVMX_BGXX_SPUX_MISC_CONTROL(offset, block_id) \ argument
316 (0x00011800E0010218ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
317 #define CVMX_BGXX_SPUX_SPD_ABIL(offset, block_id) \ argument
318 (0x00011800E0010010ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
319 #define CVMX_BGXX_SPUX_STATUS1(offset, block_id) \ argument
320 (0x00011800E0010008ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
321 #define CVMX_BGXX_SPUX_STATUS2(offset, block_id) \ argument
322 (0x00011800E0010020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576)
323 #define CVMX_BGXX_SPU_BIST_STATUS(offset) (0x00011800E0010318ull + ((offset) & 7) * 0x1000000ull) argument
324 #define CVMX_BGXX_SPU_DBG_CONTROL(offset) (0x00011800E0010300ull + ((offset) & 7) * 0x1000000ull) argument
325 #define CVMX_BGXX_SPU_MEM_INT(offset) (0x00011800E0010310ull + ((offset) & 7) * 0x1000000ull) argument
326 #define CVMX_BGXX_SPU_MEM_STATUS(offset) (0x00011800E0010308ull + ((offset) & 7) * 0x1000000ull) argument
327 #define CVMX_BGXX_SPU_SDSX_SKEW_STATUS(offset, block_id) \ argument
328 (0x00011800E0010320ull + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8)
329 #define CVMX_BGXX_SPU_SDSX_STATES(offset, block_id) \ argument
330 (0x00011800E0010340ull + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8)