Lines Matching refs:offset
14 #define CVMX_DTX_AGL_DATX(offset) (0x00011800FE700040ull + ((offset) & 1) * 8) argument
15 #define CVMX_DTX_AGL_ENAX(offset) (0x00011800FE700020ull + ((offset) & 1) * 8) argument
16 #define CVMX_DTX_AGL_SELX(offset) (0x00011800FE700000ull + ((offset) & 1) * 8) argument
19 #define CVMX_DTX_ASE_DATX(offset) (0x00011800FE6E8040ull + ((offset) & 1) * 8) argument
20 #define CVMX_DTX_ASE_ENAX(offset) (0x00011800FE6E8020ull + ((offset) & 1) * 8) argument
21 #define CVMX_DTX_ASE_SELX(offset) (0x00011800FE6E8000ull + ((offset) & 1) * 8) argument
24 #define CVMX_DTX_BBX1I_DATX(offset) (0x00011800FED78040ull + ((offset) & 1) * 8) argument
25 #define CVMX_DTX_BBX1I_ENAX(offset) (0x00011800FED78020ull + ((offset) & 1) * 8) argument
26 #define CVMX_DTX_BBX1I_SELX(offset) (0x00011800FED78000ull + ((offset) & 1) * 8) argument
29 #define CVMX_DTX_BBX2I_DATX(offset) (0x00011800FED80040ull + ((offset) & 1) * 8) argument
30 #define CVMX_DTX_BBX2I_ENAX(offset) (0x00011800FED80020ull + ((offset) & 1) * 8) argument
31 #define CVMX_DTX_BBX2I_SELX(offset) (0x00011800FED80000ull + ((offset) & 1) * 8) argument
34 #define CVMX_DTX_BBX3I_DATX(offset) (0x00011800FED88040ull + ((offset) & 1) * 8) argument
35 #define CVMX_DTX_BBX3I_ENAX(offset) (0x00011800FED88020ull + ((offset) & 1) * 8) argument
36 #define CVMX_DTX_BBX3I_SELX(offset) (0x00011800FED88000ull + ((offset) & 1) * 8) argument
39 #define CVMX_DTX_BCH_DATX(offset) (0x00011800FE388040ull + ((offset) & 1) * 8) argument
40 #define CVMX_DTX_BCH_ENAX(offset) (0x00011800FE388020ull + ((offset) & 1) * 8) argument
41 #define CVMX_DTX_BCH_SELX(offset) (0x00011800FE388000ull + ((offset) & 1) * 8) argument
42 #define CVMX_DTX_BGXX_BCST_RSP(offset) (0x00011800FE700080ull + ((offset) & 7) * 32768) argument
43 #define CVMX_DTX_BGXX_CTL(offset) (0x00011800FE700060ull + ((offset) & 7) * 32768) argument
44 #define CVMX_DTX_BGXX_DATX(offset, block_id) \ argument
45 (0x00011800FE700040ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
46 #define CVMX_DTX_BGXX_ENAX(offset, block_id) \ argument
47 (0x00011800FE700020ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
48 #define CVMX_DTX_BGXX_SELX(offset, block_id) \ argument
49 (0x00011800FE700000ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
51 #define CVMX_DTX_BROADCAST_ENAX(offset) (0x00011800FE7F0020ull + ((offset) & 1) * 8) argument
52 #define CVMX_DTX_BROADCAST_SELX(offset) (0x00011800FE7F0000ull + ((offset) & 1) * 8) argument
55 #define CVMX_DTX_BTS_DATX(offset) (0x00011800FE5B0040ull + ((offset) & 1) * 8) argument
56 #define CVMX_DTX_BTS_ENAX(offset) (0x00011800FE5B0020ull + ((offset) & 1) * 8) argument
57 #define CVMX_DTX_BTS_SELX(offset) (0x00011800FE5B0000ull + ((offset) & 1) * 8) argument
60 #define CVMX_DTX_CIU_DATX(offset) (0x00011800FE808040ull + ((offset) & 1) * 8) argument
61 #define CVMX_DTX_CIU_ENAX(offset) (0x00011800FE808020ull + ((offset) & 1) * 8) argument
62 #define CVMX_DTX_CIU_SELX(offset) (0x00011800FE808000ull + ((offset) & 1) * 8) argument
65 #define CVMX_DTX_DENC_DATX(offset) (0x00011800FED48040ull + ((offset) & 1) * 8) argument
66 #define CVMX_DTX_DENC_ENAX(offset) (0x00011800FED48020ull + ((offset) & 1) * 8) argument
67 #define CVMX_DTX_DENC_SELX(offset) (0x00011800FED48000ull + ((offset) & 1) * 8) argument
70 #define CVMX_DTX_DFA_DATX(offset) (0x00011800FE1B8040ull + ((offset) & 1) * 8) argument
71 #define CVMX_DTX_DFA_ENAX(offset) (0x00011800FE1B8020ull + ((offset) & 1) * 8) argument
72 #define CVMX_DTX_DFA_SELX(offset) (0x00011800FE1B8000ull + ((offset) & 1) * 8) argument
75 #define CVMX_DTX_DLFE_DATX(offset) (0x00011800FED18040ull + ((offset) & 1) * 8) argument
76 #define CVMX_DTX_DLFE_ENAX(offset) (0x00011800FED18020ull + ((offset) & 1) * 8) argument
77 #define CVMX_DTX_DLFE_SELX(offset) (0x00011800FED18000ull + ((offset) & 1) * 8) argument
80 #define CVMX_DTX_DPI_DATX(offset) (0x00011800FEEF8040ull + ((offset) & 1) * 8) argument
81 #define CVMX_DTX_DPI_ENAX(offset) (0x00011800FEEF8020ull + ((offset) & 1) * 8) argument
82 #define CVMX_DTX_DPI_SELX(offset) (0x00011800FEEF8000ull + ((offset) & 1) * 8) argument
83 #define CVMX_DTX_FDEQX_BCST_RSP(offset) (0x00011800FED30080ull + ((offset) & 1) * 0x20000ull) argument
84 #define CVMX_DTX_FDEQX_CTL(offset) (0x00011800FED30060ull + ((offset) & 1) * 0x20000ull) argument
85 #define CVMX_DTX_FDEQX_DATX(offset, block_id) \ argument
86 (0x00011800FED30040ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)
87 #define CVMX_DTX_FDEQX_ENAX(offset, block_id) \ argument
88 (0x00011800FED30020ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)
89 #define CVMX_DTX_FDEQX_SELX(offset, block_id) \ argument
90 (0x00011800FED30000ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)
127 static inline u64 CVMX_DTX_FPA_DATX(unsigned long offset) in CVMX_DTX_FPA_DATX() argument
133 return 0x00011800FE940040ull + (offset) * 8; in CVMX_DTX_FPA_DATX()
135 return 0x00011800FE940040ull + (offset) * 8; in CVMX_DTX_FPA_DATX()
137 return 0x00011800FE940040ull + (offset) * 8; in CVMX_DTX_FPA_DATX()
139 return 0x00011800FE140040ull + (offset) * 8; in CVMX_DTX_FPA_DATX()
141 return 0x00011800FE940040ull + (offset) * 8; in CVMX_DTX_FPA_DATX()
144 static inline u64 CVMX_DTX_FPA_ENAX(unsigned long offset) in CVMX_DTX_FPA_ENAX() argument
150 return 0x00011800FE940020ull + (offset) * 8; in CVMX_DTX_FPA_ENAX()
152 return 0x00011800FE940020ull + (offset) * 8; in CVMX_DTX_FPA_ENAX()
154 return 0x00011800FE940020ull + (offset) * 8; in CVMX_DTX_FPA_ENAX()
156 return 0x00011800FE140020ull + (offset) * 8; in CVMX_DTX_FPA_ENAX()
158 return 0x00011800FE940020ull + (offset) * 8; in CVMX_DTX_FPA_ENAX()
161 static inline u64 CVMX_DTX_FPA_SELX(unsigned long offset) in CVMX_DTX_FPA_SELX() argument
167 return 0x00011800FE940000ull + (offset) * 8; in CVMX_DTX_FPA_SELX()
169 return 0x00011800FE940000ull + (offset) * 8; in CVMX_DTX_FPA_SELX()
171 return 0x00011800FE940000ull + (offset) * 8; in CVMX_DTX_FPA_SELX()
173 return 0x00011800FE140000ull + (offset) * 8; in CVMX_DTX_FPA_SELX()
175 return 0x00011800FE940000ull + (offset) * 8; in CVMX_DTX_FPA_SELX()
178 #define CVMX_DTX_GMXX_BCST_RSP(offset) (0x00011800FE040080ull + ((offset) & 1) * 0x40000ull) argument
179 #define CVMX_DTX_GMXX_CTL(offset) (0x00011800FE040060ull + ((offset) & 1) * 0x40000ull) argument
180 #define CVMX_DTX_GMXX_DATX(offset, block_id) \ argument
181 (0x00011800FE040040ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
182 #define CVMX_DTX_GMXX_ENAX(offset, block_id) \ argument
183 (0x00011800FE040020ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
184 #define CVMX_DTX_GMXX_SELX(offset, block_id) \ argument
185 (0x00011800FE040000ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
186 #define CVMX_DTX_GSERX_BCST_RSP(offset) (0x00011800FE480080ull + ((offset) & 15) * 32768) argument
187 #define CVMX_DTX_GSERX_CTL(offset) (0x00011800FE480060ull + ((offset) & 15) * 32768) argument
188 #define CVMX_DTX_GSERX_DATX(offset, block_id) \ argument
189 (0x00011800FE480040ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)
190 #define CVMX_DTX_GSERX_ENAX(offset, block_id) \ argument
191 (0x00011800FE480020ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)
192 #define CVMX_DTX_GSERX_SELX(offset, block_id) \ argument
193 (0x00011800FE480000ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)
196 #define CVMX_DTX_HNA_DATX(offset) (0x00011800FE238040ull + ((offset) & 1) * 8) argument
197 #define CVMX_DTX_HNA_ENAX(offset) (0x00011800FE238020ull + ((offset) & 1) * 8) argument
198 #define CVMX_DTX_HNA_SELX(offset) (0x00011800FE238000ull + ((offset) & 1) * 8) argument
201 #define CVMX_DTX_ILA_DATX(offset) (0x00011800FE0B8040ull + ((offset) & 1) * 8) argument
202 #define CVMX_DTX_ILA_ENAX(offset) (0x00011800FE0B8020ull + ((offset) & 1) * 8) argument
203 #define CVMX_DTX_ILA_SELX(offset) (0x00011800FE0B8000ull + ((offset) & 1) * 8) argument
206 #define CVMX_DTX_ILK_DATX(offset) (0x00011800FE0A0040ull + ((offset) & 1) * 8) argument
207 #define CVMX_DTX_ILK_ENAX(offset) (0x00011800FE0A0020ull + ((offset) & 1) * 8) argument
208 #define CVMX_DTX_ILK_SELX(offset) (0x00011800FE0A0000ull + ((offset) & 1) * 8) argument
211 #define CVMX_DTX_IOBN_DATX(offset) (0x00011800FE780040ull + ((offset) & 1) * 8) argument
212 #define CVMX_DTX_IOBN_ENAX(offset) (0x00011800FE780020ull + ((offset) & 1) * 8) argument
213 #define CVMX_DTX_IOBN_SELX(offset) (0x00011800FE780000ull + ((offset) & 1) * 8) argument
216 #define CVMX_DTX_IOBP_DATX(offset) (0x00011800FE7A0040ull + ((offset) & 1) * 8) argument
217 #define CVMX_DTX_IOBP_ENAX(offset) (0x00011800FE7A0020ull + ((offset) & 1) * 8) argument
218 #define CVMX_DTX_IOBP_SELX(offset) (0x00011800FE7A0000ull + ((offset) & 1) * 8) argument
221 #define CVMX_DTX_IOB_DATX(offset) (0x00011800FE780040ull + ((offset) & 1) * 8) argument
222 #define CVMX_DTX_IOB_ENAX(offset) (0x00011800FE780020ull + ((offset) & 1) * 8) argument
223 #define CVMX_DTX_IOB_SELX(offset) (0x00011800FE780000ull + ((offset) & 1) * 8) argument
226 #define CVMX_DTX_IPD_DATX(offset) (0x00011800FE278040ull + ((offset) & 1) * 8) argument
227 #define CVMX_DTX_IPD_ENAX(offset) (0x00011800FE278020ull + ((offset) & 1) * 8) argument
228 #define CVMX_DTX_IPD_SELX(offset) (0x00011800FE278000ull + ((offset) & 1) * 8) argument
231 #define CVMX_DTX_KEY_DATX(offset) (0x00011800FE100040ull + ((offset) & 1) * 8) argument
232 #define CVMX_DTX_KEY_ENAX(offset) (0x00011800FE100020ull + ((offset) & 1) * 8) argument
233 #define CVMX_DTX_KEY_SELX(offset) (0x00011800FE100000ull + ((offset) & 1) * 8) argument
234 #define CVMX_DTX_L2C_CBCX_BCST_RSP(offset) (0x00011800FE420080ull + ((offset) & 3) * 32768) argument
235 #define CVMX_DTX_L2C_CBCX_CTL(offset) (0x00011800FE420060ull + ((offset) & 3) * 32768) argument
236 #define CVMX_DTX_L2C_CBCX_DATX(offset, block_id) \ argument
237 (0x00011800FE420040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
238 #define CVMX_DTX_L2C_CBCX_ENAX(offset, block_id) \ argument
239 (0x00011800FE420020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
240 #define CVMX_DTX_L2C_CBCX_SELX(offset, block_id) \ argument
241 (0x00011800FE420000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
242 #define CVMX_DTX_L2C_MCIX_BCST_RSP(offset) (0x00011800FE2E0080ull + ((offset) & 3) * 32768) argument
243 #define CVMX_DTX_L2C_MCIX_CTL(offset) (0x00011800FE2E0060ull + ((offset) & 3) * 32768) argument
244 #define CVMX_DTX_L2C_MCIX_DATX(offset, block_id) \ argument
245 (0x00011800FE2E0040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
246 #define CVMX_DTX_L2C_MCIX_ENAX(offset, block_id) \ argument
247 (0x00011800FE2E0020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
248 #define CVMX_DTX_L2C_MCIX_SELX(offset, block_id) \ argument
249 (0x00011800FE2E0000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
250 #define CVMX_DTX_L2C_TADX_BCST_RSP(offset) (0x00011800FE240080ull + ((offset) & 7) * 32768) argument
251 #define CVMX_DTX_L2C_TADX_CTL(offset) (0x00011800FE240060ull + ((offset) & 7) * 32768) argument
252 #define CVMX_DTX_L2C_TADX_DATX(offset, block_id) \ argument
253 (0x00011800FE240040ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
254 #define CVMX_DTX_L2C_TADX_ENAX(offset, block_id) \ argument
255 (0x00011800FE240020ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
256 #define CVMX_DTX_L2C_TADX_SELX(offset, block_id) \ argument
257 (0x00011800FE240000ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
258 #define CVMX_DTX_LAPX_BCST_RSP(offset) (0x00011800FE060080ull + ((offset) & 1) * 32768) argument
259 #define CVMX_DTX_LAPX_CTL(offset) (0x00011800FE060060ull + ((offset) & 1) * 32768) argument
260 #define CVMX_DTX_LAPX_DATX(offset, block_id) \ argument
261 (0x00011800FE060040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
262 #define CVMX_DTX_LAPX_ENAX(offset, block_id) \ argument
263 (0x00011800FE060020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
264 #define CVMX_DTX_LAPX_SELX(offset, block_id) \ argument
265 (0x00011800FE060000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
268 #define CVMX_DTX_LBK_DATX(offset) (0x00011800FE090040ull + ((offset) & 1) * 8) argument
269 #define CVMX_DTX_LBK_ENAX(offset) (0x00011800FE090020ull + ((offset) & 1) * 8) argument
270 #define CVMX_DTX_LBK_SELX(offset) (0x00011800FE090000ull + ((offset) & 1) * 8) argument
271 #define CVMX_DTX_LMCX_BCST_RSP(offset) (0x00011800FE440080ull + ((offset) & 3) * 32768) argument
272 #define CVMX_DTX_LMCX_CTL(offset) (0x00011800FE440060ull + ((offset) & 3) * 32768) argument
273 #define CVMX_DTX_LMCX_DATX(offset, block_id) \ argument
274 (0x00011800FE440040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
275 #define CVMX_DTX_LMCX_ENAX(offset, block_id) \ argument
276 (0x00011800FE440020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
277 #define CVMX_DTX_LMCX_SELX(offset, block_id) \ argument
278 (0x00011800FE440000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
279 #define CVMX_DTX_MDBX_BCST_RSP(offset) (0x00011800FEC00080ull + ((offset) & 31) * 32768) argument
280 #define CVMX_DTX_MDBX_CTL(offset) (0x00011800FEC00060ull + ((offset) & 31) * 32768) argument
281 #define CVMX_DTX_MDBX_DATX(offset, block_id) \ argument
282 (0x00011800FEC00040ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)
283 #define CVMX_DTX_MDBX_ENAX(offset, block_id) \ argument
284 (0x00011800FEC00020ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)
285 #define CVMX_DTX_MDBX_SELX(offset, block_id) \ argument
286 (0x00011800FEC00000ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)
289 #define CVMX_DTX_MHBW_DATX(offset) (0x00011800FE598040ull + ((offset) & 1) * 8) argument
290 #define CVMX_DTX_MHBW_ENAX(offset) (0x00011800FE598020ull + ((offset) & 1) * 8) argument
291 #define CVMX_DTX_MHBW_SELX(offset) (0x00011800FE598000ull + ((offset) & 1) * 8) argument
294 #define CVMX_DTX_MIO_DATX(offset) (0x00011800FE000040ull + ((offset) & 1) * 8) argument
295 #define CVMX_DTX_MIO_ENAX(offset) (0x00011800FE000020ull + ((offset) & 1) * 8) argument
296 #define CVMX_DTX_MIO_SELX(offset) (0x00011800FE000000ull + ((offset) & 1) * 8) argument
299 #define CVMX_DTX_OCX_BOT_DATX(offset) (0x00011800FE198040ull + ((offset) & 1) * 8) argument
300 #define CVMX_DTX_OCX_BOT_ENAX(offset) (0x00011800FE198020ull + ((offset) & 1) * 8) argument
301 #define CVMX_DTX_OCX_BOT_SELX(offset) (0x00011800FE198000ull + ((offset) & 1) * 8) argument
302 #define CVMX_DTX_OCX_LNKX_BCST_RSP(offset) (0x00011800FE180080ull + ((offset) & 3) * 32768) argument
303 #define CVMX_DTX_OCX_LNKX_CTL(offset) (0x00011800FE180060ull + ((offset) & 3) * 32768) argument
304 #define CVMX_DTX_OCX_LNKX_DATX(offset, block_id) \ argument
305 (0x00011800FE180040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
306 #define CVMX_DTX_OCX_LNKX_ENAX(offset, block_id) \ argument
307 (0x00011800FE180020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
308 #define CVMX_DTX_OCX_LNKX_SELX(offset, block_id) \ argument
309 (0x00011800FE180000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
310 #define CVMX_DTX_OCX_OLEX_BCST_RSP(offset) (0x00011800FE1A0080ull + ((offset) & 3) * 32768) argument
311 #define CVMX_DTX_OCX_OLEX_CTL(offset) (0x00011800FE1A0060ull + ((offset) & 3) * 32768) argument
312 #define CVMX_DTX_OCX_OLEX_DATX(offset, block_id) \ argument
313 (0x00011800FE1A0040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
314 #define CVMX_DTX_OCX_OLEX_ENAX(offset, block_id) \ argument
315 (0x00011800FE1A0020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
316 #define CVMX_DTX_OCX_OLEX_SELX(offset, block_id) \ argument
317 (0x00011800FE1A0000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
320 #define CVMX_DTX_OCX_TOP_DATX(offset) (0x00011800FE088040ull + ((offset) & 1) * 8) argument
321 #define CVMX_DTX_OCX_TOP_ENAX(offset) (0x00011800FE088020ull + ((offset) & 1) * 8) argument
322 #define CVMX_DTX_OCX_TOP_SELX(offset) (0x00011800FE088000ull + ((offset) & 1) * 8) argument
355 static inline u64 CVMX_DTX_OSM_DATX(unsigned long offset) in CVMX_DTX_OSM_DATX() argument
360 return 0x00011800FE6E0040ull + (offset) * 8; in CVMX_DTX_OSM_DATX()
362 return 0x00011800FE6E0040ull + (offset) * 8; in CVMX_DTX_OSM_DATX()
365 return 0x00011800FEEE0040ull + (offset) * 8; in CVMX_DTX_OSM_DATX()
367 return 0x00011800FE6E0040ull + (offset) * 8; in CVMX_DTX_OSM_DATX()
370 static inline u64 CVMX_DTX_OSM_ENAX(unsigned long offset) in CVMX_DTX_OSM_ENAX() argument
375 return 0x00011800FE6E0020ull + (offset) * 8; in CVMX_DTX_OSM_ENAX()
377 return 0x00011800FE6E0020ull + (offset) * 8; in CVMX_DTX_OSM_ENAX()
380 return 0x00011800FEEE0020ull + (offset) * 8; in CVMX_DTX_OSM_ENAX()
382 return 0x00011800FE6E0020ull + (offset) * 8; in CVMX_DTX_OSM_ENAX()
385 static inline u64 CVMX_DTX_OSM_SELX(unsigned long offset) in CVMX_DTX_OSM_SELX() argument
390 return 0x00011800FE6E0000ull + (offset) * 8; in CVMX_DTX_OSM_SELX()
392 return 0x00011800FE6E0000ull + (offset) * 8; in CVMX_DTX_OSM_SELX()
395 return 0x00011800FEEE0000ull + (offset) * 8; in CVMX_DTX_OSM_SELX()
397 return 0x00011800FE6E0000ull + (offset) * 8; in CVMX_DTX_OSM_SELX()
400 #define CVMX_DTX_PCSX_BCST_RSP(offset) (0x00011800FE580080ull + ((offset) & 1) * 0x40000ull) argument
401 #define CVMX_DTX_PCSX_CTL(offset) (0x00011800FE580060ull + ((offset) & 1) * 0x40000ull) argument
402 #define CVMX_DTX_PCSX_DATX(offset, block_id) \ argument
403 (0x00011800FE580040ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
404 #define CVMX_DTX_PCSX_ENAX(offset, block_id) \ argument
405 (0x00011800FE580020ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
406 #define CVMX_DTX_PCSX_SELX(offset, block_id) \ argument
407 (0x00011800FE580000ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
408 #define CVMX_DTX_PEMX_BCST_RSP(offset) (0x00011800FE600080ull + ((offset) & 3) * 32768) argument
409 #define CVMX_DTX_PEMX_CTL(offset) (0x00011800FE600060ull + ((offset) & 3) * 32768) argument
410 #define CVMX_DTX_PEMX_DATX(offset, block_id) \ argument
411 (0x00011800FE600040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
412 #define CVMX_DTX_PEMX_ENAX(offset, block_id) \ argument
413 (0x00011800FE600020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
414 #define CVMX_DTX_PEMX_SELX(offset, block_id) \ argument
415 (0x00011800FE600000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
418 #define CVMX_DTX_PIP_DATX(offset) (0x00011800FE500040ull + ((offset) & 1) * 8) argument
419 #define CVMX_DTX_PIP_ENAX(offset) (0x00011800FE500020ull + ((offset) & 1) * 8) argument
420 #define CVMX_DTX_PIP_SELX(offset) (0x00011800FE500000ull + ((offset) & 1) * 8) argument
423 #define CVMX_DTX_PKI_PBE_DATX(offset) (0x00011800FE228040ull + ((offset) & 1) * 8) argument
424 #define CVMX_DTX_PKI_PBE_ENAX(offset) (0x00011800FE228020ull + ((offset) & 1) * 8) argument
425 #define CVMX_DTX_PKI_PBE_SELX(offset) (0x00011800FE228000ull + ((offset) & 1) * 8) argument
428 #define CVMX_DTX_PKI_PFE_DATX(offset) (0x00011800FE220040ull + ((offset) & 1) * 8) argument
429 #define CVMX_DTX_PKI_PFE_ENAX(offset) (0x00011800FE220020ull + ((offset) & 1) * 8) argument
430 #define CVMX_DTX_PKI_PFE_SELX(offset) (0x00011800FE220000ull + ((offset) & 1) * 8) argument
433 #define CVMX_DTX_PKI_PIX_DATX(offset) (0x00011800FE230040ull + ((offset) & 1) * 8) argument
434 #define CVMX_DTX_PKI_PIX_ENAX(offset) (0x00011800FE230020ull + ((offset) & 1) * 8) argument
435 #define CVMX_DTX_PKI_PIX_SELX(offset) (0x00011800FE230000ull + ((offset) & 1) * 8) argument
472 static inline u64 CVMX_DTX_PKO_DATX(unsigned long offset) in CVMX_DTX_PKO_DATX() argument
478 return 0x00011800FEAA0040ull + (offset) * 8; in CVMX_DTX_PKO_DATX()
480 return 0x00011800FEAA0040ull + (offset) * 8; in CVMX_DTX_PKO_DATX()
482 return 0x00011800FEAA0040ull + (offset) * 8; in CVMX_DTX_PKO_DATX()
484 return 0x00011800FE280040ull + (offset) * 8; in CVMX_DTX_PKO_DATX()
486 return 0x00011800FEAA0040ull + (offset) * 8; in CVMX_DTX_PKO_DATX()
489 static inline u64 CVMX_DTX_PKO_ENAX(unsigned long offset) in CVMX_DTX_PKO_ENAX() argument
495 return 0x00011800FEAA0020ull + (offset) * 8; in CVMX_DTX_PKO_ENAX()
497 return 0x00011800FEAA0020ull + (offset) * 8; in CVMX_DTX_PKO_ENAX()
499 return 0x00011800FEAA0020ull + (offset) * 8; in CVMX_DTX_PKO_ENAX()
501 return 0x00011800FE280020ull + (offset) * 8; in CVMX_DTX_PKO_ENAX()
503 return 0x00011800FEAA0020ull + (offset) * 8; in CVMX_DTX_PKO_ENAX()
506 static inline u64 CVMX_DTX_PKO_SELX(unsigned long offset) in CVMX_DTX_PKO_SELX() argument
512 return 0x00011800FEAA0000ull + (offset) * 8; in CVMX_DTX_PKO_SELX()
514 return 0x00011800FEAA0000ull + (offset) * 8; in CVMX_DTX_PKO_SELX()
516 return 0x00011800FEAA0000ull + (offset) * 8; in CVMX_DTX_PKO_SELX()
518 return 0x00011800FE280000ull + (offset) * 8; in CVMX_DTX_PKO_SELX()
520 return 0x00011800FEAA0000ull + (offset) * 8; in CVMX_DTX_PKO_SELX()
523 #define CVMX_DTX_PNBDX_BCST_RSP(offset) (0x00011800FED90080ull + ((offset) & 1) * 32768) argument
524 #define CVMX_DTX_PNBDX_CTL(offset) (0x00011800FED90060ull + ((offset) & 1) * 32768) argument
525 #define CVMX_DTX_PNBDX_DATX(offset, block_id) \ argument
526 (0x00011800FED90040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
527 #define CVMX_DTX_PNBDX_ENAX(offset, block_id) \ argument
528 (0x00011800FED90020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
529 #define CVMX_DTX_PNBDX_SELX(offset, block_id) \ argument
530 (0x00011800FED90000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
531 #define CVMX_DTX_PNBX_BCST_RSP(offset) (0x00011800FE580080ull + ((offset) & 1) * 32768) argument
532 #define CVMX_DTX_PNBX_CTL(offset) (0x00011800FE580060ull + ((offset) & 1) * 32768) argument
533 #define CVMX_DTX_PNBX_DATX(offset, block_id) \ argument
534 (0x00011800FE580040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
535 #define CVMX_DTX_PNBX_ENAX(offset, block_id) \ argument
536 (0x00011800FE580020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
537 #define CVMX_DTX_PNBX_SELX(offset, block_id) \ argument
538 (0x00011800FE580000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
541 #define CVMX_DTX_POW_DATX(offset) (0x00011800FE338040ull + ((offset) & 1) * 8) argument
542 #define CVMX_DTX_POW_ENAX(offset) (0x00011800FE338020ull + ((offset) & 1) * 8) argument
543 #define CVMX_DTX_POW_SELX(offset) (0x00011800FE338000ull + ((offset) & 1) * 8) argument
546 #define CVMX_DTX_PRCH_DATX(offset) (0x00011800FED00040ull + ((offset) & 1) * 8) argument
547 #define CVMX_DTX_PRCH_ENAX(offset) (0x00011800FED00020ull + ((offset) & 1) * 8) argument
548 #define CVMX_DTX_PRCH_SELX(offset) (0x00011800FED00000ull + ((offset) & 1) * 8) argument
551 #define CVMX_DTX_PSM_DATX(offset) (0x00011800FEEA0040ull + ((offset) & 1) * 8) argument
552 #define CVMX_DTX_PSM_ENAX(offset) (0x00011800FEEA0020ull + ((offset) & 1) * 8) argument
553 #define CVMX_DTX_PSM_SELX(offset) (0x00011800FEEA0000ull + ((offset) & 1) * 8) argument
556 #define CVMX_DTX_RAD_DATX(offset) (0x00011800FE380040ull + ((offset) & 1) * 8) argument
557 #define CVMX_DTX_RAD_ENAX(offset) (0x00011800FE380020ull + ((offset) & 1) * 8) argument
558 #define CVMX_DTX_RAD_SELX(offset) (0x00011800FE380000ull + ((offset) & 1) * 8) argument
561 #define CVMX_DTX_RDEC_DATX(offset) (0x00011800FED68040ull + ((offset) & 1) * 8) argument
562 #define CVMX_DTX_RDEC_ENAX(offset) (0x00011800FED68020ull + ((offset) & 1) * 8) argument
563 #define CVMX_DTX_RDEC_SELX(offset) (0x00011800FED68000ull + ((offset) & 1) * 8) argument
566 #define CVMX_DTX_RFIF_DATX(offset) (0x00011800FE6A8040ull + ((offset) & 1) * 8) argument
567 #define CVMX_DTX_RFIF_ENAX(offset) (0x00011800FE6A8020ull + ((offset) & 1) * 8) argument
568 #define CVMX_DTX_RFIF_SELX(offset) (0x00011800FE6A8000ull + ((offset) & 1) * 8) argument
571 #define CVMX_DTX_RMAP_DATX(offset) (0x00011800FED40040ull + ((offset) & 1) * 8) argument
572 #define CVMX_DTX_RMAP_ENAX(offset) (0x00011800FED40020ull + ((offset) & 1) * 8) argument
573 #define CVMX_DTX_RMAP_SELX(offset) (0x00011800FED40000ull + ((offset) & 1) * 8) argument
576 #define CVMX_DTX_RNM_DATX(offset) (0x00011800FE200040ull + ((offset) & 1) * 8) argument
577 #define CVMX_DTX_RNM_ENAX(offset) (0x00011800FE200020ull + ((offset) & 1) * 8) argument
578 #define CVMX_DTX_RNM_SELX(offset) (0x00011800FE200000ull + ((offset) & 1) * 8) argument
581 #define CVMX_DTX_RST_DATX(offset) (0x00011800FE030040ull + ((offset) & 1) * 8) argument
582 #define CVMX_DTX_RST_ENAX(offset) (0x00011800FE030020ull + ((offset) & 1) * 8) argument
583 #define CVMX_DTX_RST_SELX(offset) (0x00011800FE030000ull + ((offset) & 1) * 8) argument
586 #define CVMX_DTX_SATA_DATX(offset) (0x00011800FE360040ull + ((offset) & 1) * 8) argument
587 #define CVMX_DTX_SATA_ENAX(offset) (0x00011800FE360020ull + ((offset) & 1) * 8) argument
588 #define CVMX_DTX_SATA_SELX(offset) (0x00011800FE360000ull + ((offset) & 1) * 8) argument
591 #define CVMX_DTX_SLI_DATX(offset) (0x00011800FE8F8040ull + ((offset) & 1) * 8) argument
592 #define CVMX_DTX_SLI_ENAX(offset) (0x00011800FE8F8020ull + ((offset) & 1) * 8) argument
593 #define CVMX_DTX_SLI_SELX(offset) (0x00011800FE8F8000ull + ((offset) & 1) * 8) argument
596 #define CVMX_DTX_SPEM_DATX(offset) (0x00011800FE600040ull + ((offset) & 1) * 8) argument
597 #define CVMX_DTX_SPEM_ENAX(offset) (0x00011800FE600020ull + ((offset) & 1) * 8) argument
598 #define CVMX_DTX_SPEM_SELX(offset) (0x00011800FE600000ull + ((offset) & 1) * 8) argument
599 #define CVMX_DTX_SRIOX_BCST_RSP(offset) (0x00011800FE640080ull + ((offset) & 1) * 32768) argument
600 #define CVMX_DTX_SRIOX_CTL(offset) (0x00011800FE640060ull + ((offset) & 1) * 32768) argument
601 #define CVMX_DTX_SRIOX_DATX(offset, block_id) \ argument
602 (0x00011800FE640040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
603 #define CVMX_DTX_SRIOX_ENAX(offset, block_id) \ argument
604 (0x00011800FE640020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
605 #define CVMX_DTX_SRIOX_SELX(offset, block_id) \ argument
606 (0x00011800FE640000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
609 #define CVMX_DTX_SSO_DATX(offset) (0x00011800FEB38040ull + ((offset) & 1) * 8) argument
610 #define CVMX_DTX_SSO_ENAX(offset) (0x00011800FEB38020ull + ((offset) & 1) * 8) argument
611 #define CVMX_DTX_SSO_SELX(offset) (0x00011800FEB38000ull + ((offset) & 1) * 8) argument
614 #define CVMX_DTX_TDEC_DATX(offset) (0x00011800FED60040ull + ((offset) & 1) * 8) argument
615 #define CVMX_DTX_TDEC_ENAX(offset) (0x00011800FED60020ull + ((offset) & 1) * 8) argument
616 #define CVMX_DTX_TDEC_SELX(offset) (0x00011800FED60000ull + ((offset) & 1) * 8) argument
619 #define CVMX_DTX_TIM_DATX(offset) (0x00011800FE2C0040ull + ((offset) & 1) * 8) argument
620 #define CVMX_DTX_TIM_ENAX(offset) (0x00011800FE2C0020ull + ((offset) & 1) * 8) argument
621 #define CVMX_DTX_TIM_SELX(offset) (0x00011800FE2C0000ull + ((offset) & 1) * 8) argument
624 #define CVMX_DTX_ULFE_DATX(offset) (0x00011800FED08040ull + ((offset) & 1) * 8) argument
625 #define CVMX_DTX_ULFE_ENAX(offset) (0x00011800FED08020ull + ((offset) & 1) * 8) argument
626 #define CVMX_DTX_ULFE_SELX(offset) (0x00011800FED08000ull + ((offset) & 1) * 8) argument
627 #define CVMX_DTX_USBDRDX_BCST_RSP(offset) (0x00011800FE340080ull + ((offset) & 1) * 32768) argument
628 #define CVMX_DTX_USBDRDX_CTL(offset) (0x00011800FE340060ull + ((offset) & 1) * 32768) argument
629 #define CVMX_DTX_USBDRDX_DATX(offset, block_id) \ argument
630 (0x00011800FE340040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
631 #define CVMX_DTX_USBDRDX_ENAX(offset, block_id) \ argument
632 (0x00011800FE340020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
633 #define CVMX_DTX_USBDRDX_SELX(offset, block_id) \ argument
634 (0x00011800FE340000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
635 #define CVMX_DTX_USBHX_BCST_RSP(offset) (0x00011800FE340080ull) argument
636 #define CVMX_DTX_USBHX_CTL(offset) (0x00011800FE340060ull) argument
637 #define CVMX_DTX_USBHX_DATX(offset, block_id) \ argument
638 (0x00011800FE340040ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
639 #define CVMX_DTX_USBHX_ENAX(offset, block_id) \ argument
640 (0x00011800FE340020ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
641 #define CVMX_DTX_USBHX_SELX(offset, block_id) \ argument
642 (0x00011800FE340000ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
645 #define CVMX_DTX_VDEC_DATX(offset) (0x00011800FED70040ull + ((offset) & 1) * 8) argument
646 #define CVMX_DTX_VDEC_ENAX(offset) (0x00011800FED70020ull + ((offset) & 1) * 8) argument
647 #define CVMX_DTX_VDEC_SELX(offset) (0x00011800FED70000ull + ((offset) & 1) * 8) argument
650 #define CVMX_DTX_WPSE_DATX(offset) (0x00011800FED10040ull + ((offset) & 1) * 8) argument
651 #define CVMX_DTX_WPSE_ENAX(offset) (0x00011800FED10020ull + ((offset) & 1) * 8) argument
652 #define CVMX_DTX_WPSE_SELX(offset) (0x00011800FED10000ull + ((offset) & 1) * 8) argument
655 #define CVMX_DTX_WRCE_DATX(offset) (0x00011800FED38040ull + ((offset) & 1) * 8) argument
656 #define CVMX_DTX_WRCE_ENAX(offset) (0x00011800FED38020ull + ((offset) & 1) * 8) argument
657 #define CVMX_DTX_WRCE_SELX(offset) (0x00011800FED38000ull + ((offset) & 1) * 8) argument
660 #define CVMX_DTX_WRDE_DATX(offset) (0x00011800FED58040ull + ((offset) & 1) * 8) argument
661 #define CVMX_DTX_WRDE_ENAX(offset) (0x00011800FED58020ull + ((offset) & 1) * 8) argument
662 #define CVMX_DTX_WRDE_SELX(offset) (0x00011800FED58000ull + ((offset) & 1) * 8) argument
665 #define CVMX_DTX_WRSE_DATX(offset) (0x00011800FED28040ull + ((offset) & 1) * 8) argument
666 #define CVMX_DTX_WRSE_ENAX(offset) (0x00011800FED28020ull + ((offset) & 1) * 8) argument
667 #define CVMX_DTX_WRSE_SELX(offset) (0x00011800FED28000ull + ((offset) & 1) * 8) argument
670 #define CVMX_DTX_WTXE_DATX(offset) (0x00011800FED20040ull + ((offset) & 1) * 8) argument
671 #define CVMX_DTX_WTXE_ENAX(offset) (0x00011800FED20020ull + ((offset) & 1) * 8) argument
672 #define CVMX_DTX_WTXE_SELX(offset) (0x00011800FED20000ull + ((offset) & 1) * 8) argument
675 #define CVMX_DTX_XCV_DATX(offset) (0x00011800FE6D8040ull + ((offset) & 1) * 8) argument
676 #define CVMX_DTX_XCV_ENAX(offset) (0x00011800FE6D8020ull + ((offset) & 1) * 8) argument
677 #define CVMX_DTX_XCV_SELX(offset) (0x00011800FE6D8000ull + ((offset) & 1) * 8) argument
680 #define CVMX_DTX_XSX_DATX(offset) (0x00011800FE5A8040ull + ((offset) & 1) * 8) argument
681 #define CVMX_DTX_XSX_ENAX(offset) (0x00011800FE5A8020ull + ((offset) & 1) * 8) argument
682 #define CVMX_DTX_XSX_SELX(offset) (0x00011800FE5A8000ull + ((offset) & 1) * 8) argument
685 #define CVMX_DTX_ZIP_DATX(offset) (0x00011800FE1C0040ull + ((offset) & 1) * 8) argument
686 #define CVMX_DTX_ZIP_ENAX(offset) (0x00011800FE1C0020ull + ((offset) & 1) * 8) argument
687 #define CVMX_DTX_ZIP_SELX(offset) (0x00011800FE1C0000ull + ((offset) & 1) * 8) argument