Lines Matching refs:ddr
35 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
38 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
42 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
44 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
49 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) in board_add_ram_info()
55 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) in board_add_ram_info()
134 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
165 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); in spd_sdram()
228 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
229 ddr->cs_config[0] = ( 1 << 31 in spd_sdram()
236 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); in spd_sdram()
237 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); in spd_sdram()
240 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) in spd_sdram()
242 ddr->cs_config[1] = ( 1<<31 in spd_sdram()
248 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); in spd_sdram()
249 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); in spd_sdram()
253 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
254 ddr->cs_config[2] = ( 1 << 31 in spd_sdram()
261 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); in spd_sdram()
262 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); in spd_sdram()
265 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) in spd_sdram()
267 ddr->cs_config[3] = ( 1<<31 in spd_sdram()
273 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); in spd_sdram()
274 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); in spd_sdram()
440 ddr->debug_reg = 0x201c0000; /* CL=2 */ in spd_sdram()
442 ddr->debug_reg = 0x202c0000; /* CL=2.5 */ in spd_sdram()
444 ddr->debug_reg = 0x202c0000; /* CL=3.0 */ in spd_sdram()
448 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); in spd_sdram()
475 ddr->timing_cfg_0 = (0 in spd_sdram()
481 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in spd_sdram()
538 ddr->timing_cfg_1 = in spd_sdram()
630 ddr->timing_cfg_2 = (0 in spd_sdram()
640 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); in spd_sdram()
641 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); in spd_sdram()
667 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ in spd_sdram()
670 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ in spd_sdram()
673 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ in spd_sdram()
676 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ in spd_sdram()
693 ddr->sdram_mode = in spd_sdram()
706 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); in spd_sdram()
711 ddr->sdram_mode2 = 0; in spd_sdram()
712 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); in spd_sdram()
748 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; in spd_sdram()
749 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); in spd_sdram()
761 ddr->sdram_cfg2 = (0 in spd_sdram()
767 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); in spd_sdram()
771 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in spd_sdram()
773 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); in spd_sdram()
825 ddr->err_disable = ~ECC_ERROR_ENABLE; in spd_sdram()
828 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | in spd_sdram()
832 debug("DDR:err_disable=0x%08x\n", ddr->err_disable); in spd_sdram()
833 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); in spd_sdram()
838 ddr->sdram_cfg = sdram_cfg; in spd_sdram()
843 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); in spd_sdram()
900 volatile ddr83xx_t *ddr= &immap->ddr; in ddr_enable_ecc() local
925 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME) in ddr_enable_ecc()
926 ddr->err_detect |= ECC_ERROR_DETECT_MME; in ddr_enable_ecc()
927 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE) in ddr_enable_ecc()
928 ddr->err_detect |= ECC_ERROR_DETECT_MBE; in ddr_enable_ecc()
929 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE) in ddr_enable_ecc()
930 ddr->err_detect |= ECC_ERROR_DETECT_SBE; in ddr_enable_ecc()
931 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE) in ddr_enable_ecc()
932 ddr->err_detect |= ECC_ERROR_DETECT_MSE; in ddr_enable_ecc()
935 ddr->err_int_en &= ECC_ERR_INT_DISABLE; in ddr_enable_ecc()
938 ddr->err_disable &= ECC_ERROR_ENABLE; in ddr_enable_ecc()