Lines Matching refs:ddr
76 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
77 out_be32(&im->ddr.cs_config[0], config); in fixed_sdram()
80 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
81 out_be32(&im->ddr.cs_config[2], 0); in fixed_sdram()
82 out_be32(&im->ddr.cs_config[3], 0); in fixed_sdram()
84 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
85 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
86 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
87 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
89 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); in fixed_sdram()
90 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); in fixed_sdram()
92 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
93 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); in fixed_sdram()
95 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); in fixed_sdram()
96 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); in fixed_sdram()
101 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()