Lines Matching refs:src_clk_div
367 int src_clk_div; in rk3328_i2c_set_clk() local
369 src_clk_div = GPLL_HZ / hz; in rk3328_i2c_set_clk()
370 assert(src_clk_div - 1 < 127); in rk3328_i2c_set_clk()
377 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
384 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
391 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
398 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
406 return DIV_TO_RATE(GPLL_HZ, src_clk_div); in rk3328_i2c_set_clk()
476 int src_clk_div; in rk3328_mmc_set_clk() local
493 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3328_mmc_set_clk()
495 if (src_clk_div > 127) { in rk3328_mmc_set_clk()
497 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3328_mmc_set_clk()
501 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); in rk3328_mmc_set_clk()
506 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); in rk3328_mmc_set_clk()
547 int src_clk_div; in rk3328_saradc_set_clk() local
549 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
550 assert(src_clk_div < 128); in rk3328_saradc_set_clk()
554 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); in rk3328_saradc_set_clk()
571 u32 src_clk_div; in rk3328_spi_set_clk() local
573 src_clk_div = GPLL_HZ / hz; in rk3328_spi_set_clk()
574 assert(src_clk_div < 128); in rk3328_spi_set_clk()
579 (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT); in rk3328_spi_set_clk()