Lines Matching refs:src_clk
748 int src_clk; in rk3568_bus_set_clk() local
753 src_clk = ACLK_BUS_SEL_200M; in rk3568_bus_set_clk()
755 src_clk = ACLK_BUS_SEL_150M; in rk3568_bus_set_clk()
757 src_clk = ACLK_BUS_SEL_100M; in rk3568_bus_set_clk()
759 src_clk = ACLK_BUS_SEL_24M; in rk3568_bus_set_clk()
762 src_clk << ACLK_BUS_SEL_SHIFT); in rk3568_bus_set_clk()
767 src_clk = PCLK_BUS_SEL_100M; in rk3568_bus_set_clk()
769 src_clk = PCLK_BUS_SEL_75M; in rk3568_bus_set_clk()
771 src_clk = PCLK_BUS_SEL_50M; in rk3568_bus_set_clk()
773 src_clk = PCLK_BUS_SEL_24M; in rk3568_bus_set_clk()
776 src_clk << PCLK_BUS_SEL_SHIFT); in rk3568_bus_set_clk()
828 int src_clk; in rk3568_perimid_set_clk() local
833 src_clk = ACLK_PERIMID_SEL_300M; in rk3568_perimid_set_clk()
835 src_clk = ACLK_PERIMID_SEL_200M; in rk3568_perimid_set_clk()
837 src_clk = ACLK_PERIMID_SEL_100M; in rk3568_perimid_set_clk()
839 src_clk = ACLK_PERIMID_SEL_24M; in rk3568_perimid_set_clk()
842 src_clk << ACLK_PERIMID_SEL_SHIFT); in rk3568_perimid_set_clk()
846 src_clk = HCLK_PERIMID_SEL_150M; in rk3568_perimid_set_clk()
848 src_clk = HCLK_PERIMID_SEL_100M; in rk3568_perimid_set_clk()
850 src_clk = HCLK_PERIMID_SEL_75M; in rk3568_perimid_set_clk()
852 src_clk = HCLK_PERIMID_SEL_24M; in rk3568_perimid_set_clk()
855 src_clk << HCLK_PERIMID_SEL_SHIFT); in rk3568_perimid_set_clk()
931 int src_clk; in rk3568_top_set_clk() local
936 src_clk = ACLK_TOP_HIGH_SEL_500M; in rk3568_top_set_clk()
938 src_clk = ACLK_TOP_HIGH_SEL_400M; in rk3568_top_set_clk()
940 src_clk = ACLK_TOP_HIGH_SEL_300M; in rk3568_top_set_clk()
942 src_clk = ACLK_TOP_HIGH_SEL_24M; in rk3568_top_set_clk()
945 src_clk << ACLK_TOP_HIGH_SEL_SHIFT); in rk3568_top_set_clk()
949 src_clk = ACLK_TOP_LOW_SEL_400M; in rk3568_top_set_clk()
951 src_clk = ACLK_TOP_LOW_SEL_300M; in rk3568_top_set_clk()
953 src_clk = ACLK_TOP_LOW_SEL_200M; in rk3568_top_set_clk()
955 src_clk = ACLK_TOP_LOW_SEL_24M; in rk3568_top_set_clk()
958 src_clk << ACLK_TOP_LOW_SEL_SHIFT); in rk3568_top_set_clk()
962 src_clk = HCLK_TOP_SEL_150M; in rk3568_top_set_clk()
964 src_clk = HCLK_TOP_SEL_100M; in rk3568_top_set_clk()
966 src_clk = HCLK_TOP_SEL_75M; in rk3568_top_set_clk()
968 src_clk = HCLK_TOP_SEL_24M; in rk3568_top_set_clk()
971 src_clk << HCLK_TOP_SEL_SHIFT); in rk3568_top_set_clk()
975 src_clk = PCLK_TOP_SEL_100M; in rk3568_top_set_clk()
977 src_clk = PCLK_TOP_SEL_75M; in rk3568_top_set_clk()
979 src_clk = PCLK_TOP_SEL_50M; in rk3568_top_set_clk()
981 src_clk = PCLK_TOP_SEL_24M; in rk3568_top_set_clk()
984 src_clk << PCLK_TOP_SEL_SHIFT); in rk3568_top_set_clk()
1029 int src_clk; in rk3568_i2c_set_clk() local
1032 src_clk = CLK_I2C_SEL_200M; in rk3568_i2c_set_clk()
1034 src_clk = CLK_I2C_SEL_100M; in rk3568_i2c_set_clk()
1036 src_clk = CLK_I2C_SEL_24M; in rk3568_i2c_set_clk()
1045 src_clk << CLK_I2C_SEL_SHIFT); in rk3568_i2c_set_clk()
1094 int src_clk; in rk3568_spi_set_clk() local
1097 src_clk = CLK_SPI_SEL_200M; in rk3568_spi_set_clk()
1099 src_clk = CLK_SPI_SEL_CPLL_100M; in rk3568_spi_set_clk()
1101 src_clk = CLK_SPI_SEL_24M; in rk3568_spi_set_clk()
1107 src_clk << CLK_SPI0_SEL_SHIFT); in rk3568_spi_set_clk()
1112 src_clk << CLK_SPI1_SEL_SHIFT); in rk3568_spi_set_clk()
1117 src_clk << CLK_SPI2_SEL_SHIFT); in rk3568_spi_set_clk()
1122 src_clk << CLK_SPI3_SEL_SHIFT); in rk3568_spi_set_clk()
1168 int src_clk; in rk3568_pwm_set_clk() local
1171 src_clk = CLK_PWM_SEL_100M; in rk3568_pwm_set_clk()
1173 src_clk = CLK_PWM_SEL_24M; in rk3568_pwm_set_clk()
1179 src_clk << CLK_PWM1_SEL_SHIFT); in rk3568_pwm_set_clk()
1184 src_clk << CLK_PWM2_SEL_SHIFT); in rk3568_pwm_set_clk()
1189 src_clk << CLK_PWM3_SEL_SHIFT); in rk3568_pwm_set_clk()
1336 u32 src_clk, mask, shift; in rk3568_crypto_set_rate() local
1344 src_clk = ACLK_SECURE_FLASH_SEL_200M; in rk3568_crypto_set_rate()
1346 src_clk = ACLK_SECURE_FLASH_SEL_150M; in rk3568_crypto_set_rate()
1348 src_clk = ACLK_SECURE_FLASH_SEL_100M; in rk3568_crypto_set_rate()
1350 src_clk = ACLK_SECURE_FLASH_SEL_24M; in rk3568_crypto_set_rate()
1358 src_clk = HCLK_SECURE_FLASH_SEL_150M; in rk3568_crypto_set_rate()
1360 src_clk = HCLK_SECURE_FLASH_SEL_100M; in rk3568_crypto_set_rate()
1362 src_clk = HCLK_SECURE_FLASH_SEL_75M; in rk3568_crypto_set_rate()
1364 src_clk = HCLK_SECURE_FLASH_SEL_24M; in rk3568_crypto_set_rate()
1370 src_clk = CLK_CRYPTO_CORE_SEL_200M; in rk3568_crypto_set_rate()
1372 src_clk = CLK_CRYPTO_CORE_SEL_150M; in rk3568_crypto_set_rate()
1374 src_clk = CLK_CRYPTO_CORE_SEL_100M; in rk3568_crypto_set_rate()
1380 src_clk = CLK_CRYPTO_PKA_SEL_300M; in rk3568_crypto_set_rate()
1382 src_clk = CLK_CRYPTO_PKA_SEL_200M; in rk3568_crypto_set_rate()
1384 src_clk = CLK_CRYPTO_PKA_SEL_100M; in rk3568_crypto_set_rate()
1390 rk_clrsetreg(&cru->clksel_con[27], mask, src_clk << shift); in rk3568_crypto_set_rate()
1440 int src_clk; in rk3568_sdmmc_set_clk() local
1445 src_clk = CLK_SDMMC_SEL_24M; in rk3568_sdmmc_set_clk()
1448 src_clk = CLK_SDMMC_SEL_400M; in rk3568_sdmmc_set_clk()
1451 src_clk = CLK_SDMMC_SEL_300M; in rk3568_sdmmc_set_clk()
1454 src_clk = CLK_SDMMC_SEL_100M; in rk3568_sdmmc_set_clk()
1458 src_clk = CLK_SDMMC_SEL_50M; in rk3568_sdmmc_set_clk()
1462 src_clk = CLK_SDMMC_SEL_750K; in rk3568_sdmmc_set_clk()
1473 src_clk << CLK_SDMMC0_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1478 src_clk << CLK_SDMMC1_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1483 src_clk << CLK_SDMMC2_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1520 int src_clk; in rk3568_sfc_set_clk() local
1524 src_clk = SCLK_SFC_SEL_24M; in rk3568_sfc_set_clk()
1527 src_clk = SCLK_SFC_SEL_50M; in rk3568_sfc_set_clk()
1530 src_clk = SCLK_SFC_SEL_75M; in rk3568_sfc_set_clk()
1533 src_clk = SCLK_SFC_SEL_100M; in rk3568_sfc_set_clk()
1536 src_clk = SCLK_SFC_SEL_125M; in rk3568_sfc_set_clk()
1539 src_clk = SCLK_SFC_SEL_150M; in rk3568_sfc_set_clk()
1547 src_clk << SCLK_SFC_SEL_SHIFT); in rk3568_sfc_set_clk()
1576 int src_clk; in rk3568_nand_set_clk() local
1580 src_clk = NCLK_NANDC_SEL_24M; in rk3568_nand_set_clk()
1583 src_clk = NCLK_NANDC_SEL_100M; in rk3568_nand_set_clk()
1586 src_clk = NCLK_NANDC_SEL_150M; in rk3568_nand_set_clk()
1589 src_clk = NCLK_NANDC_SEL_200M; in rk3568_nand_set_clk()
1597 src_clk << NCLK_NANDC_SEL_SHIFT); in rk3568_nand_set_clk()
1630 int src_clk; in rk3568_emmc_set_clk() local
1634 src_clk = CCLK_EMMC_SEL_24M; in rk3568_emmc_set_clk()
1638 src_clk = CCLK_EMMC_SEL_50M; in rk3568_emmc_set_clk()
1641 src_clk = CCLK_EMMC_SEL_100M; in rk3568_emmc_set_clk()
1644 src_clk = CCLK_EMMC_SEL_150M; in rk3568_emmc_set_clk()
1647 src_clk = CCLK_EMMC_SEL_200M; in rk3568_emmc_set_clk()
1651 src_clk = CCLK_EMMC_SEL_375K; in rk3568_emmc_set_clk()
1659 src_clk << CCLK_EMMC_SEL_SHIFT); in rk3568_emmc_set_clk()
1686 int src_clk; in rk3568_emmc_set_bclk() local
1690 src_clk = BCLK_EMMC_SEL_200M; in rk3568_emmc_set_bclk()
1693 src_clk = BCLK_EMMC_SEL_150M; in rk3568_emmc_set_bclk()
1696 src_clk = BCLK_EMMC_SEL_125M; in rk3568_emmc_set_bclk()
1704 src_clk << BCLK_EMMC_SEL_SHIFT); in rk3568_emmc_set_bclk()
1896 int src_clk; in rk3568_gmac_src_set_clk() local
1900 src_clk = CLK_MAC0_2TOP_SEL_125M; in rk3568_gmac_src_set_clk()
1903 src_clk = CLK_MAC0_2TOP_SEL_50M; in rk3568_gmac_src_set_clk()
1906 src_clk = CLK_MAC0_2TOP_SEL_25M; in rk3568_gmac_src_set_clk()
1914 src_clk << CLK_MAC0_2TOP_SEL_SHIFT); in rk3568_gmac_src_set_clk()
1946 int src_clk; in rk3568_gmac_out_set_clk() local
1950 src_clk = CLK_MAC0_OUT_SEL_125M; in rk3568_gmac_out_set_clk()
1953 src_clk = CLK_MAC0_OUT_SEL_50M; in rk3568_gmac_out_set_clk()
1956 src_clk = CLK_MAC0_OUT_SEL_25M; in rk3568_gmac_out_set_clk()
1959 src_clk = CLK_MAC0_OUT_SEL_24M; in rk3568_gmac_out_set_clk()
1967 src_clk << CLK_MAC0_OUT_SEL_SHIFT); in rk3568_gmac_out_set_clk()
1999 int src_clk; in rk3568_gmac_ptp_ref_set_clk() local
2003 src_clk = CLK_GMAC0_PTP_REF_SEL_62_5M; in rk3568_gmac_ptp_ref_set_clk()
2006 src_clk = CLK_GMAC0_PTP_REF_SEL_100M; in rk3568_gmac_ptp_ref_set_clk()
2009 src_clk = CLK_GMAC0_PTP_REF_SEL_50M; in rk3568_gmac_ptp_ref_set_clk()
2012 src_clk = CLK_GMAC0_PTP_REF_SEL_24M; in rk3568_gmac_ptp_ref_set_clk()
2020 src_clk << CLK_GMAC0_PTP_REF_SEL_SHIFT); in rk3568_gmac_ptp_ref_set_clk()