Lines Matching refs:src_clk_div
247 int src_clk_div; in rk3568_i2c_set_pmuclk() local
249 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_i2c_set_pmuclk()
250 assert(src_clk_div - 1 <= 127); in rk3568_i2c_set_pmuclk()
255 (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); in rk3568_i2c_set_pmuclk()
291 int src_clk_div; in rk3568_pwm_set_pmuclk() local
302 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pwm_set_pmuclk()
303 assert(src_clk_div - 1 <= 127); in rk3568_pwm_set_pmuclk()
307 (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); in rk3568_pwm_set_pmuclk()
337 int src_clk_div; in rk3568_pmu_set_pmuclk() local
339 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pmu_set_pmuclk()
340 assert(src_clk_div - 1 <= 31); in rk3568_pmu_set_pmuclk()
345 ((src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT)); in rk3568_pmu_set_pmuclk()
1231 int src_clk_div; in rk3568_adc_set_clk() local
1239 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3568_adc_set_clk()
1240 assert(src_clk_div - 1 <= 7); in rk3568_adc_set_clk()
1246 (src_clk_div - 1) << in rk3568_adc_set_clk()
1249 src_clk_div = DIV_ROUND_UP(100 * MHz, rate); in rk3568_adc_set_clk()
1250 assert(src_clk_div - 1 <= 7); in rk3568_adc_set_clk()
1256 (src_clk_div - 1) << in rk3568_adc_set_clk()
1262 src_clk_div = DIV_ROUND_UP(prate, rate); in rk3568_adc_set_clk()
1263 assert(src_clk_div - 1 <= 128); in rk3568_adc_set_clk()
1266 (src_clk_div - 1) << CLK_TSADC_DIV_SHIFT); in rk3568_adc_set_clk()
1733 int src_clk_div, src_clk_mux; in rk3568_aclk_vop_set_clk() local
1736 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_aclk_vop_set_clk()
1739 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_aclk_vop_set_clk()
1742 assert(src_clk_div - 1 <= 31); in rk3568_aclk_vop_set_clk()
1746 (src_clk_div - 1) << ACLK_VOP_PRE_DIV_SHIFT); in rk3568_aclk_vop_set_clk()
2083 int src_clk_div; in rk3568_ebc_set_clk() local
2085 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_ebc_set_clk()
2086 assert(src_clk_div - 1 <= 31); in rk3568_ebc_set_clk()
2089 (src_clk_div - 1) << CPLL_333M_DIV_SHIFT); in rk3568_ebc_set_clk()
2137 int src_clk_div, src, p_rate; in rk3568_rkvdec_set_clk() local
2148 src_clk_div = DIV_ROUND_UP(p_rate, rate); in rk3568_rkvdec_set_clk()
2149 assert(src_clk_div - 1 <= 31); in rk3568_rkvdec_set_clk()
2154 (src_clk_div - 1) << ACLK_RKVDEC_DIV_SHIFT); in rk3568_rkvdec_set_clk()
2167 src_clk_div = DIV_ROUND_UP(p_rate, rate); in rk3568_rkvdec_set_clk()
2168 assert(src_clk_div - 1 <= 31); in rk3568_rkvdec_set_clk()
2173 (src_clk_div - 1) << CLK_RKVDEC_CORE_DIV_SHIFT); in rk3568_rkvdec_set_clk()