Lines Matching refs:ddr
57 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
87 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
91 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
96 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
101 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
114 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
117 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
119 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
124 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
126 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
130 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
131 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
133 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
137 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
140 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
142 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
143 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
147 ddr_out32(&ddr->cs2_bnds, in fsl_ddr_set_memctl_regs()
150 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
152 ddr_out32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
153 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
157 ddr_out32(&ddr->cs3_bnds, in fsl_ddr_set_memctl_regs()
160 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
162 ddr_out32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
163 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
167 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
168 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
169 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
170 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
171 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
172 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
173 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); in fsl_ddr_set_memctl_regs()
174 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); in fsl_ddr_set_memctl_regs()
175 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); in fsl_ddr_set_memctl_regs()
176 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); in fsl_ddr_set_memctl_regs()
177 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
178 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); in fsl_ddr_set_memctl_regs()
179 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); in fsl_ddr_set_memctl_regs()
180 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); in fsl_ddr_set_memctl_regs()
181 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); in fsl_ddr_set_memctl_regs()
182 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); in fsl_ddr_set_memctl_regs()
183 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
184 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); in fsl_ddr_set_memctl_regs()
185 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); in fsl_ddr_set_memctl_regs()
186 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); in fsl_ddr_set_memctl_regs()
187 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); in fsl_ddr_set_memctl_regs()
188 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); in fsl_ddr_set_memctl_regs()
189 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); in fsl_ddr_set_memctl_regs()
190 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); in fsl_ddr_set_memctl_regs()
191 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); in fsl_ddr_set_memctl_regs()
192 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); in fsl_ddr_set_memctl_regs()
193 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); in fsl_ddr_set_memctl_regs()
194 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); in fsl_ddr_set_memctl_regs()
195 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); in fsl_ddr_set_memctl_regs()
196 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); in fsl_ddr_set_memctl_regs()
197 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); in fsl_ddr_set_memctl_regs()
198 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); in fsl_ddr_set_memctl_regs()
199 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); in fsl_ddr_set_memctl_regs()
201 ddr_out32(&ddr->sdram_interval, in fsl_ddr_set_memctl_regs()
204 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
206 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); in fsl_ddr_set_memctl_regs()
207 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
215 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); in fsl_ddr_set_memctl_regs()
217 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
220 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
221 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); in fsl_ddr_set_memctl_regs()
222 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); in fsl_ddr_set_memctl_regs()
223 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); in fsl_ddr_set_memctl_regs()
224 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); in fsl_ddr_set_memctl_regs()
225 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); in fsl_ddr_set_memctl_regs()
226 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); in fsl_ddr_set_memctl_regs()
229 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
231 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); in fsl_ddr_set_memctl_regs()
232 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); in fsl_ddr_set_memctl_regs()
235 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
240 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
241 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
242 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); in fsl_ddr_set_memctl_regs()
243 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
250 ddr_out32(&ddr->ddr_sdram_rcw_2, in fsl_ddr_set_memctl_regs()
253 ddr_out32(&ddr->err_disable, regs->err_disable | in fsl_ddr_set_memctl_regs()
257 ddr_out32(&ddr->err_disable, regs->err_disable); in fsl_ddr_set_memctl_regs()
259 ddr_out32(&ddr->err_int_en, regs->err_int_en); in fsl_ddr_set_memctl_regs()
264 ddr_out32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
272 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
275 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
277 ddr_out32(&ddr->debug[28], temp32); in fsl_ddr_set_memctl_regs()
278 ddr_out32(&ddr->debug[25], 0x9000); in fsl_ddr_set_memctl_regs()
281 ddr_out32(&ddr->debug[37], 1 << 31); in fsl_ddr_set_memctl_regs()
283 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
293 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
298 temp32 = ddr_in32(&ddr->debug[25]); in fsl_ddr_set_memctl_regs()
301 ddr_out32(&ddr->debug[25], temp32); in fsl_ddr_set_memctl_regs()
307 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
308 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000); in fsl_ddr_set_memctl_regs()
328 ddr_out32(&ddr->sdram_cfg, temp32); in fsl_ddr_set_memctl_regs()
343 temp32 = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
345 ddr_out32(&ddr->sdram_cfg_2, temp32); in fsl_ddr_set_memctl_regs()
349 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
352 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; in fsl_ddr_set_memctl_regs()
354 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
363 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && in fsl_ddr_set_memctl_regs()
370 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
391 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
396 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
401 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
406 ddr_out32(&ddr->sdram_md_cntl, 0); in fsl_ddr_set_memctl_regs()
407 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
409 ddr_out32(&ddr->debug[28], temp32); in fsl_ddr_set_memctl_regs()
410 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ in fsl_ddr_set_memctl_regs()
413 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && in fsl_ddr_set_memctl_regs()
420 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
432 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
441 ddr_out32(&ddr->err_disable, in fsl_ddr_set_memctl_regs()
446 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
456 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
458 ddr_out32(&ddr->debug[28], val32); in fsl_ddr_set_memctl_regs()
465 val32 = ddr_in32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */ in fsl_ddr_set_memctl_regs()
466 ddr_out32(&ddr->sdram_cfg_2, val32); in fsl_ddr_set_memctl_regs()
468 val32 = ddr_in32(&ddr->debug[18]) | 0x2; in fsl_ddr_set_memctl_regs()
469 ddr_out32(&ddr->debug[18], val32); in fsl_ddr_set_memctl_regs()
471 ddr_out32(&ddr->debug[28], 0x30000000); in fsl_ddr_set_memctl_regs()
477 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
488 ddr_out32(&ddr->debug[28], val32); in fsl_ddr_set_memctl_regs()
512 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
521 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
532 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds); in fsl_ddr_set_memctl_regs()
534 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds); in fsl_ddr_set_memctl_regs()
536 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds); in fsl_ddr_set_memctl_regs()
538 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds); in fsl_ddr_set_memctl_regs()
542 ddr_out32(&ddr->cs0_config, regs->cs[0].config); in fsl_ddr_set_memctl_regs()
546 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
552 temp32 = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
554 ddr_out32(&ddr->sdram_cfg_2, temp32); in fsl_ddr_set_memctl_regs()
568 cs0_config = ddr_in32(&ddr->cs0_config); in fsl_ddr_set_memctl_regs()
569 cs0_bnds = ddr_in32(&ddr->cs0_bnds); in fsl_ddr_set_memctl_regs()
570 cs1_bnds = ddr_in32(&ddr->cs1_bnds); in fsl_ddr_set_memctl_regs()
571 cs2_bnds = ddr_in32(&ddr->cs2_bnds); in fsl_ddr_set_memctl_regs()
572 cs3_bnds = ddr_in32(&ddr->cs3_bnds); in fsl_ddr_set_memctl_regs()
575 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
576 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
577 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
578 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
580 ddr_out32(&ddr->mtp1, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
581 ddr_out32(&ddr->mtp2, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
582 ddr_out32(&ddr->mtp3, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
583 ddr_out32(&ddr->mtp4, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
584 ddr_out32(&ddr->mtp5, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
585 ddr_out32(&ddr->mtp6, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
586 ddr_out32(&ddr->mtp7, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
587 ddr_out32(&ddr->mtp8, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
588 ddr_out32(&ddr->mtp9, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
589 ddr_out32(&ddr->mtp10, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
591 ddr_out32(&ddr->mtcr, mtcr); in fsl_ddr_set_memctl_regs()
596 mtcr = ddr_in32(&ddr->mtcr); in fsl_ddr_set_memctl_regs()
602 err_detect = ddr_in32(&ddr->err_detect); in fsl_ddr_set_memctl_regs()
603 err_sbe = ddr_in32(&ddr->err_sbe); in fsl_ddr_set_memctl_regs()
615 ddr_out32(&ddr->cs0_bnds, cs0_bnds); in fsl_ddr_set_memctl_regs()
616 ddr_out32(&ddr->cs1_bnds, cs1_bnds); in fsl_ddr_set_memctl_regs()
617 ddr_out32(&ddr->cs2_bnds, cs2_bnds); in fsl_ddr_set_memctl_regs()
618 ddr_out32(&ddr->cs3_bnds, cs3_bnds); in fsl_ddr_set_memctl_regs()