Lines Matching refs:ddr
20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
47 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
48 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
49 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
73 struct ccsr_ddr __iomem *ddr = in ddr_enable_ecc() local
81 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); in ddr_enable_ecc()
82 ddr->err_disable = 0x00000000; in ddr_enable_ecc()
84 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); in ddr_enable_ecc()