Lines Matching refs:dev_num
185 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
191 static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) in ddr3_ctrl_get_junc_temp() argument
225 static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum mv_ddr_freq freq, in ddr3_tip_a38x_get_freq_config() argument
365 static int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable) in ddr3_tip_a38x_select_ddr_controller() argument
389 static int mv_ddr_sar_freq_get(int dev_num, enum mv_ddr_freq *freq) in mv_ddr_sar_freq_get() argument
483 static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) in ddr3_tip_a38x_get_medium_freq() argument
560 static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) in ddr3_tip_a38x_get_device_info() argument
636 static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) in mv_ddr_sw_db_init() argument
656 ddr3_tip_init_config_func(dev_num, &config_func); in mv_ddr_sw_db_init()
658 ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin); in mv_ddr_sw_db_init()
661 ddr3_tip_dev_attr_init(dev_num); in mv_ddr_sw_db_init()
662 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_TIP_REV, MV_TIP_REV_4); in mv_ddr_sw_db_init()
663 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE); in mv_ddr_sw_db_init()
664 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_OCTET_PER_INTERFACE, DDR_INTERFACE_OCTETS_NUM); in mv_ddr_sw_db_init()
665 ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 0); in mv_ddr_sw_db_init()
672 ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq); in mv_ddr_sw_db_init()
731 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, in ddr3_tip_a38x_set_divider() argument
846 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_read() argument
860 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_write() argument
1368 int ddr3_tip_configure_phy(u32 dev_num) in ddr3_tip_configure_phy() argument
1371 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_configure_phy()
1375 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1380 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1385 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1390 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1396 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1400 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1404 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1418 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_configure_phy()
1425 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_configure_phy()
1431 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_PHY_EDGE) == in ddr3_tip_configure_phy()
1434 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()