Lines Matching refs:eth

94 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,  in fec_mdio_read()  argument
106 	writel(FEC_IEVENT_MII, &eth->ievent);  in fec_mdio_read()
111 			phy | reg, &eth->mii_data);  in fec_mdio_read()
115 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {  in fec_mdio_read()
123 	writel(FEC_IEVENT_MII, &eth->ievent);  in fec_mdio_read()
126 	val = (unsigned short)readl(&eth->mii_data);  in fec_mdio_read()
166 static void fec_mii_setspeed(struct ethernet_regs *eth)  in fec_mii_setspeed()  argument
200 	writel(speed << 1 | hold << 8, &eth->mii_speed);  in fec_mii_setspeed()
201 	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));  in fec_mii_setspeed()
204 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,  in fec_mdio_write()  argument
215 		FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);  in fec_mdio_write()
219 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {  in fec_mdio_write()
227 	writel(FEC_IEVENT_MII, &eth->ievent);  in fec_mdio_write()
252 	struct ethernet_regs *eth = fec->bus->priv;  in miiphy_restart_aneg()  local
259 	fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);  in miiphy_restart_aneg()
261 	fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);  in miiphy_restart_aneg()
265 	fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,  in miiphy_restart_aneg()
268 	fec_mdio_write(eth, fec->phy_id, MII_BMCR,  in miiphy_restart_aneg()
284 	struct ethernet_regs *eth = fec->bus->priv;  in miiphy_wait_aneg()  local
294 		status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);  in miiphy_wait_aneg()
309 	writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);  in fec_rx_task_enable()
320 	writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);  in fec_tx_task_enable()
426 	writel(0, &fec->eth->iaddr1);  in fecmxc_set_hwaddr()
427 	writel(0, &fec->eth->iaddr2);  in fecmxc_set_hwaddr()
428 	writel(0, &fec->eth->gaddr1);  in fecmxc_set_hwaddr()
429 	writel(0, &fec->eth->gaddr2);  in fecmxc_set_hwaddr()
433 	       &fec->eth->paddr1);  in fecmxc_set_hwaddr()
434 	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);  in fecmxc_set_hwaddr()
445 	writel(0x00000000, &fec->eth->imask);  in fec_reg_setup()
448 	writel(0xffffffff, &fec->eth->ievent);  in fec_reg_setup()
464 	writel(rcntrl, &fec->eth->r_cntrl);  in fec_reg_setup()
488 	writel(1 << 2, &fec->eth->x_cntrl);  in fec_open()
504 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,  in fec_open()
505 	       &fec->eth->ecntrl);  in fec_open()
507 	writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,  in fec_open()
508 	       &fec->eth->x_wmrk);  in fec_open()
511 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,  in fec_open()
512 	       &fec->eth->ecntrl);  in fec_open()
515 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,  in fec_open()
516 	       &fec->eth->ecntrl);  in fec_open()
520 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,  in fec_open()
521 	       &fec->eth->ecntrl);  in fec_open()
529 	writew(0, &fec->eth->miigsk_enr);  in fec_open()
532 	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)  in fec_open()
536 	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);  in fec_open()
539 	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);  in fec_open()
543 	while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {  in fec_open()
573 		u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;  in fec_open()
574 		u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;  in fec_open()
579 		writel(ecr, &fec->eth->ecntrl);  in fec_open()
580 		writel(rcr, &fec->eth->r_cntrl);  in fec_open()
603 	u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;  in fecmxc_init()
626 	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */  in fecmxc_init()
627 	writel(0x2, &fec->eth->x_wmrk);  in fecmxc_init()
630 	writel(0x00000000, &fec->eth->gaddr1);  in fecmxc_init()
631 	writel(0x00000000, &fec->eth->gaddr2);  in fecmxc_init()
640 		writel(0x520, &fec->eth->r_fstart);  in fecmxc_init()
644 	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);  in fecmxc_init()
647 	writel((uint32_t)addr, &fec->eth->etdsr);  in fecmxc_init()
650 	writel((uint32_t)addr, &fec->eth->erdsr);  in fecmxc_init()
678 	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),  in fecmxc_halt()
679 	       &fec->eth->x_cntrl);  in fecmxc_halt()
683 	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))  in fecmxc_halt()
694 	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,  in fecmxc_halt()
695 	       &fec->eth->ecntrl);  in fecmxc_halt()
807 		if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))  in fecmxc_send()
888 	ievent = readl(&fec->eth->ievent);  in fecmxc_recv()
889 	writel(ievent, &fec->eth->ievent);  in fecmxc_recv()
904 		writel(0x00000001 | readl(&fec->eth->x_cntrl),  in fecmxc_recv()
905 		       &fec->eth->x_cntrl);  in fecmxc_recv()
909 		if (readl(&fec->eth->x_cntrl) & 0x00000001) {  in fecmxc_recv()
915 			writel(~0x00000001 & readl(&fec->eth->x_cntrl),  in fecmxc_recv()
916 			       &fec->eth->x_cntrl);  in fecmxc_recv()
1083 	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;  in fec_get_miibus()  local
1094 	bus->priv = eth;  in fec_get_miibus()
1103 	fec_mii_setspeed(eth);  in fec_get_miibus()
1152 	fec->eth = (struct ethernet_regs *)(ulong)base_addr;  in fec_probe()
1158 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);  in fec_probe()
1160 	while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {  in fec_probe()
1383 		if (enet_fused((ulong)priv->eth)) {  in fecmxc_probe()
1384 			printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);  in fecmxc_probe()
1463 	writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,  in fecmxc_probe()
1464 	       &priv->eth->ecntrl);  in fecmxc_probe()
1466 	while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {  in fecmxc_probe()
1488 		bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));  in fecmxc_probe()
1564 	priv->eth = (struct ethernet_regs *)pdata->iobase;  in fecmxc_of_to_plat()