Lines Matching defs:stm32mp1_ddrctl
11 struct stm32mp1_ddrctl { struct
12 u32 mstr ; /* 0x0 Master*/
13 u32 stat; /* 0x4 Operating Mode Status*/
14 u8 reserved008[0x10 - 0x8];
15 u32 mrctrl0; /* 0x10 Control 0.*/
16 u32 mrctrl1; /* 0x14 Control 1*/
17 u32 mrstat; /* 0x18 Status*/
18 u32 reserved01c; /* 0x1c */
19 u32 derateen; /* 0x20 Temperature Derate Enable*/
20 u32 derateint; /* 0x24 Temperature Derate Interval*/
21 u8 reserved028[0x30 - 0x28];
22 u32 pwrctl; /* 0x30 Low Power Control*/
23 u32 pwrtmg; /* 0x34 Low Power Timing*/
24 u32 hwlpctl; /* 0x38 Hardware Low Power Control*/
25 u8 reserved03c[0x50 - 0x3C];
26 u32 rfshctl0; /* 0x50 Refresh Control 0*/
27 u32 reserved054; /* 0x54 Refresh Control 1*/
28 u32 reserved058; /* 0x58 Refresh Control 2*/
29 u32 reserved05C;
30 u32 rfshctl3; /* 0x60 Refresh Control 0*/
31 u32 rfshtmg; /* 0x64 Refresh Timing*/
32 u8 reserved068[0xc0 - 0x68];
33 u32 crcparctl0; /* 0xc0 CRC Parity Control0*/
34 u32 reserved0c4; /* 0xc4 CRC Parity Control1*/
35 u32 reserved0c8; /* 0xc8 CRC Parity Control2*/
36 u32 crcparstat; /* 0xcc CRC Parity Status*/
37 u32 init0; /* 0xd0 SDRAM Initialization 0*/
38 u32 init1; /* 0xd4 SDRAM Initialization 1*/
39 u32 init2; /* 0xd8 SDRAM Initialization 2*/
40 u32 init3; /* 0xdc SDRAM Initialization 3*/
41 u32 init4; /* 0xe0 SDRAM Initialization 4*/
42 u32 init5; /* 0xe4 SDRAM Initialization 5*/
43 u32 reserved0e8;
44 u32 reserved0ec;
45 u32 dimmctl; /* 0xf0 DIMM Control*/
46 u8 reserved0f4[0x100 - 0xf4];
47 u32 dramtmg0; /* 0x100 SDRAM Timing 0*/
48 u32 dramtmg1; /* 0x104 SDRAM Timing 1*/
49 u32 dramtmg2; /* 0x108 SDRAM Timing 2*/
50 u32 dramtmg3; /* 0x10c SDRAM Timing 3*/
51 u32 dramtmg4; /* 0x110 SDRAM Timing 4*/
52 u32 dramtmg5; /* 0x114 SDRAM Timing 5*/
53 u32 dramtmg6; /* 0x118 SDRAM Timing 6*/
54 u32 dramtmg7; /* 0x11c SDRAM Timing 7*/
55 u32 dramtmg8; /* 0x120 SDRAM Timing 8*/
56 u8 reserved124[0x138 - 0x124];
57 u32 dramtmg14; /* 0x138 SDRAM Timing 14*/
58 u32 dramtmg15; /* 0x13C SDRAM Timing 15*/
59 u8 reserved140[0x180 - 0x140];
60 u32 zqctl0; /* 0x180 ZQ Control 0*/
61 u32 zqctl1; /* 0x184 ZQ Control 1*/
62 u32 zqctl2; /* 0x188 ZQ Control 2*/
63 u32 zqstat; /* 0x18c ZQ Status*/
64 u32 dfitmg0; /* 0x190 DFI Timing 0*/
65 u32 dfitmg1; /* 0x194 DFI Timing 1*/
66 u32 dfilpcfg0; /* 0x198 DFI Low Power Configuration 0*/
67 u32 reserved19c;
68 u32 dfiupd0; /* 0x1a0 DFI Update 0*/
69 u32 dfiupd1; /* 0x1a4 DFI Update 1*/
70 u32 dfiupd2; /* 0x1a8 DFI Update 2*/
71 u32 reserved1ac;
72 u32 dfimisc; /* 0x1b0 DFI Miscellaneous Control*/
73 u8 reserved1b4[0x1bc - 0x1b4];
74 u32 dfistat; /* 0x1bc DFI Miscellaneous Control*/
75 u8 reserved1c0[0x1c4 - 0x1c0];
76 u32 dfiphymstr; /* 0x1c4 DFI PHY Master interface*/
77 u8 reserved1c8[0x204 - 0x1c8];
78 u32 addrmap1; /* 0x204 Address Map 1*/
79 u32 addrmap2; /* 0x208 Address Map 2*/
80 u32 addrmap3; /* 0x20c Address Map 3*/
81 u32 addrmap4; /* 0x210 Address Map 4*/
82 u32 addrmap5; /* 0x214 Address Map 5*/
83 u32 addrmap6; /* 0x218 Address Map 6*/
84 u8 reserved21c[0x224 - 0x21c];
85 u32 addrmap9; /* 0x224 Address Map 9*/
86 u32 addrmap10; /* 0x228 Address Map 10*/
87 u32 addrmap11; /* 0x22C Address Map 11*/
88 u8 reserved230[0x240 - 0x230];
89 u32 odtcfg; /* 0x240 ODT Configuration*/
90 u32 odtmap; /* 0x244 ODT/Rank Map*/
91 u8 reserved248[0x250 - 0x248];
92 u32 sched; /* 0x250 Scheduler Control*/
93 u32 sched1; /* 0x254 Scheduler Control 1*/
94 u32 reserved258;
95 u32 perfhpr1; /* 0x25c High Priority Read CAM 1*/
96 u32 reserved260;
97 u32 perflpr1; /* 0x264 Low Priority Read CAM 1*/
98 u32 reserved268;
99 u32 perfwr1; /* 0x26c Write CAM 1*/
100 u8 reserved27c[0x300 - 0x270];
101 u32 dbg0; /* 0x300 Debug 0*/
102 u32 dbg1; /* 0x304 Debug 1*/
103 u32 dbgcam; /* 0x308 CAM Debug*/
104 u32 dbgcmd; /* 0x30c Command Debug*/
105 u32 dbgstat; /* 0x310 Status Debug*/
106 u8 reserved314[0x320 - 0x314];
107 u32 swctl; /* 0x320 Software Programming Control Enable*/
108 u32 swstat; /* 0x324 Software Programming Control Status*/
109 u8 reserved328[0x36c - 0x328];
110 u32 poisoncfg; /* 0x36c AXI Poison Configuration Register*/
111 u32 poisonstat; /* 0x370 AXI Poison Status Register*/
112 u8 reserved374[0x3fc - 0x374];
115 u32 pstat; /* 0x3fc Port Status*/
116 u32 pccfg; /* 0x400 Port Common Configuration*/
119 u32 pcfgr_0; /* 0x404 Configuration Read*/
120 u32 pcfgw_0; /* 0x408 Configuration Write*/
121 u8 reserved40c[0x490 - 0x40c];
122 u32 pctrl_0; /* 0x490 Port Control Register */
123 u32 pcfgqos0_0; /* 0x494 Read QoS Configuration 0*/
124 u32 pcfgqos1_0; /* 0x498 Read QoS Configuration 1*/
125 u32 pcfgwqos0_0; /* 0x49c Write QoS Configuration 0*/
126 u32 pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1*/
127 u8 reserved4a4[0x4b4 - 0x4a4];
130 u32 pcfgr_1; /* 0x4b4 Configuration Read*/
131 u32 pcfgw_1; /* 0x4b8 Configuration Write*/
132 u8 reserved4bc[0x540 - 0x4bc];
133 u32 pctrl_1; /* 0x540 Port 2 Control Register */
134 u32 pcfgqos0_1; /* 0x544 Read QoS Configuration 0*/
135 u32 pcfgqos1_1; /* 0x548 Read QoS Configuration 1*/
136 u32 pcfgwqos0_1; /* 0x54c Write QoS Configuration 0*/
137 u32 pcfgwqos1_1; /* 0x550 Write QoS Configuration 1*/