Lines Matching refs:phy
213 static void itm_soft_reset(struct stm32mp1_ddrphy *phy) in itm_soft_reset() argument
215 stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); in itm_soft_reset()
222 static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit) in DQ_unit_index() argument
225 u32 addr = DXNDQTR(phy, byte); in DQ_unit_index()
242 static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx) in DQS_phase_delay() argument
248 clrsetbits_le32(DXNDLLCR(phy, byte), in DQS_phase_delay()
257 static void DQS_unit_delay(struct stm32mp1_ddrphy *phy, in DQS_unit_delay() argument
261 clrsetbits_le32(DXNDQSTR(phy, byte), in DQS_unit_delay()
270 stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); in DQS_unit_delay()
276 static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy, in set_DQ_unit_delay() argument
283 clrsetbits_le32(DXNDQTR(phy, byte), in set_DQ_unit_delay()
289 static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy, in set_r0dgsl_delay() argument
292 clrsetbits_le32(DXNDQSTR(phy, byte), in set_r0dgsl_delay()
297 static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy, in set_r0dgps_delay() argument
300 clrsetbits_le32(DXNDQSTR(phy, byte), in set_r0dgps_delay()
307 struct stm32mp1_ddrphy *phy) in config_BIST() argument
356 writel(0x3, &phy->bistrr); in config_BIST()
359 &phy->bistrr); in config_BIST()
363 writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */ in config_BIST()
365 writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0); in config_BIST()
366 writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1); in config_BIST()
367 writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2); in config_BIST()
371 static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8) in BIST_datx8_sel() argument
373 clrsetbits_le32(&phy->bistrr, in BIST_datx8_sel()
382 static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte, in BIST_test() argument
394 itm_soft_reset(phy); in BIST_test()
398 clrsetbits_le32(&phy->bistrr, in BIST_test()
405 writel(BIST_seed, &phy->bistlsr); in BIST_test()
407 writel(rand(), &phy->bistlsr); in BIST_test()
413 clrsetbits_le32(&phy->bistrr, in BIST_test()
419 ret = readl_poll_timeout(&phy->bistgsr, val, in BIST_test()
426 clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002); in BIST_test()
430 if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) in BIST_test()
431 == readl(&phy->bistwcr)) { in BIST_test()
434 if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR) in BIST_test()
465 static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte, in apply_deskew_results() argument
473 set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]); in apply_deskew_results()
474 index = DQ_unit_index(phy, byte, bit_i); in apply_deskew_results()
501 struct stm32mp1_ddrphy *phy, char *string) in bit_deskew() argument
525 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); in bit_deskew()
531 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); in bit_deskew()
534 clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
535 clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
536 clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
537 clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
540 config_BIST(ctl, phy); in bit_deskew()
554 setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); in bit_deskew()
557 BIST_datx8_sel(phy, datx8); in bit_deskew()
563 writel(0xAAAAAAAA, DXNDQTR(phy, datx8)); in bit_deskew()
573 DQS_unit_delay(phy, datx8, dqs_unit_delay_index); in bit_deskew()
574 DQS_phase_delay(phy, datx8, phase_idx); in bit_deskew()
577 clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST); in bit_deskew()
578 setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST); in bit_deskew()
581 BIST_test(phy, datx8, &result); in bit_deskew()
599 DQS_phase_delay(phy, datx8, phase_idx); in bit_deskew()
600 BIST_test(phy, datx8, &result); in bit_deskew()
627 DQS_phase_delay(phy, datx8, phase_idx); in bit_deskew()
633 DQS_unit_delay(phy, datx8, in bit_deskew()
635 BIST_test(phy, datx8, &result); in bit_deskew()
643 DQS_unit_delay(phy, datx8, in bit_deskew()
681 DQS_phase_delay(phy, datx8, phase_idx); in bit_deskew()
682 BIST_test(phy, datx8, &result); in bit_deskew()
707 DQS_unit_delay(phy, datx8, in bit_deskew()
709 BIST_test(phy, datx8, &result); in bit_deskew()
743 DQS_phase_delay(phy, datx8, phase_idx - 1); in bit_deskew()
749 DQS_unit_delay(phy, datx8, in bit_deskew()
751 BIST_test(phy, datx8, &result); in bit_deskew()
797 DQS_unit_delay(phy, datx8, last_right_ok.unit); in bit_deskew()
798 DQS_phase_delay(phy, datx8, last_right_ok.phase); in bit_deskew()
799 writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8)); in bit_deskew()
824 writel(0xFFFFFFFF, DXNDQTR(phy, datx8)); in bit_deskew()
834 set_DQ_unit_delay(phy, datx8, in bit_deskew()
837 BIST_test(phy, datx8, &result); in bit_deskew()
891 apply_deskew_results(phy, datx8, deskew_delay, in bit_deskew()
894 DQS_phase_delay(phy, datx8, 3); in bit_deskew()
895 DQS_unit_delay(phy, datx8, 3); in bit_deskew()
897 clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); in bit_deskew()
901 setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
902 setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
903 setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
904 setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); in bit_deskew()
919 struct stm32mp1_ddrphy *phy, char *string) in eye_training() argument
938 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); in eye_training()
944 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); in eye_training()
947 clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); in eye_training()
948 clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); in eye_training()
949 clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); in eye_training()
950 clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); in eye_training()
953 config_BIST(ctl, phy); in eye_training()
977 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN); in eye_training()
980 BIST_datx8_sel(phy, byte); in eye_training()
996 DQS_unit_delay(phy, byte, dqs_unit_delay_index); in eye_training()
997 DQS_phase_delay(phy, byte, phase_idx); in eye_training()
998 BIST_test(phy, byte, &result); in eye_training()
1005 DQS_phase_delay(phy, byte, phase_idx); in eye_training()
1006 BIST_test(phy, byte, &result); in eye_training()
1018 DQS_phase_delay(phy, byte, in eye_training()
1020 BIST_test(phy, byte, &result); in eye_training()
1045 DQS_unit_delay(phy, byte, in eye_training()
1047 DQS_phase_delay(phy, byte, in eye_training()
1049 BIST_test(phy, byte, &result); in eye_training()
1078 DQS_unit_delay(phy, byte, in eye_training()
1080 DQS_phase_delay(phy, byte, phase_idx); in eye_training()
1081 BIST_test(phy, byte, &result); in eye_training()
1115 DQS_unit_delay(phy, byte, in eye_training()
1117 DQS_phase_delay(phy, byte, phase_idx); in eye_training()
1118 BIST_test(phy, byte, &result); in eye_training()
1144 DQS_unit_delay(phy, byte, in eye_training()
1146 DQS_phase_delay(phy, byte, phase_idx); in eye_training()
1147 BIST_test(phy, byte, &result); in eye_training()
1192 DQS_phase_delay(phy, byte, eye_training_val[byte][0]); in eye_training()
1193 DQS_unit_delay(phy, byte, eye_training_val[byte][1]); in eye_training()
1209 static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte) in display_reg_results() argument
1217 printf("%d ", DQ_unit_index(phy, byte, i)); in display_reg_results()
1221 DXNDLLCR(phy, byte), in display_reg_results()
1222 readl(DXNDLLCR(phy, byte))); in display_reg_results()
1224 DXNDQSTR(phy, byte), in display_reg_results()
1225 readl(DXNDQSTR(phy, byte))); in display_reg_results()
1227 DXNDQTR(phy, byte), in display_reg_results()
1228 readl(DXNDQTR(phy, byte))); in display_reg_results()
1232 static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte, in set_midpoint_read_dqs_gating() argument
1335 set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]); in set_midpoint_read_dqs_gating()
1336 set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]); in set_midpoint_read_dqs_gating()
1347 struct stm32mp1_ddrphy *phy, in read_dqs_gating() argument
1360 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); in read_dqs_gating()
1366 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); in read_dqs_gating()
1369 clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); in read_dqs_gating()
1370 clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); in read_dqs_gating()
1371 clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); in read_dqs_gating()
1372 clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); in read_dqs_gating()
1375 config_BIST(ctl, phy); in read_dqs_gating()
1384 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN); in read_dqs_gating()
1387 BIST_datx8_sel(phy, byte); in read_dqs_gating()
1397 set_r0dgsl_delay(phy, byte, gsl_idx); in read_dqs_gating()
1398 set_r0dgps_delay(phy, byte, gps_idx); in read_dqs_gating()
1400 BIST_test(phy, byte, &result); in read_dqs_gating()
1404 itm_soft_reset(phy); in read_dqs_gating()
1407 set_midpoint_read_dqs_gating(phy, byte, dqs_gating); in read_dqs_gating()
1423 struct stm32mp1_ddrphy *phy, in do_read_dqs_gating() argument
1435 res = read_dqs_gating(ctl, phy, string); in do_read_dqs_gating()
1444 struct stm32mp1_ddrphy *phy, in do_bit_deskew() argument
1455 res = bit_deskew(ctl, phy, string); in do_bit_deskew()
1464 struct stm32mp1_ddrphy *phy, in do_eye_training() argument
1475 res = eye_training(ctl, phy, string); in do_eye_training()
1484 struct stm32mp1_ddrphy *phy, in do_display() argument
1491 display_reg_results(phy, byte); in do_display()
1497 struct stm32mp1_ddrphy *phy, in do_bist_config() argument