1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Qualcomm SPMI bus driver
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * Loosely based on Little Kernel driver
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <dm/device_compat.h>
17 #include <spmi/spmi.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* PMIC Arbiter configuration registers */
22 #define PMIC_ARB_VERSION 0x0000
23 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
24 #define PMIC_ARB_VERSION_V3_MIN 0x30000000
25 #define PMIC_ARB_VERSION_V5_MIN 0x50000000
26
27 #define APID_MAP_OFFSET_V1_V2_V3 (0x800)
28 #define APID_MAP_OFFSET_V5 (0x900)
29 #define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
30 #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
31 #define SPMI_V5_OBS_CH_OFFSET(chnl) ((chnl) * 0x80)
32 #define SPMI_V5_RW_CH_OFFSET(chnl) ((chnl) * 0x10000)
33
34 #define SPMI_REG_CMD0 0x0
35 #define SPMI_REG_CONFIG 0x4
36 #define SPMI_REG_STATUS 0x8
37 #define SPMI_REG_WDATA 0x10
38 #define SPMI_REG_RDATA 0x18
39
40 #define SPMI_CMD_OPCODE_SHIFT 27
41 #define SPMI_CMD_SLAVE_ID_SHIFT 20
42 #define SPMI_CMD_ADDR_SHIFT 12
43 #define SPMI_CMD_ADDR_OFFSET_SHIFT 4
44 #define SPMI_CMD_BYTE_CNT_SHIFT 0
45
46 #define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
47 #define SPMI_CMD_EXT_REG_READ_LONG 0x01
48
49 #define SPMI_STATUS_DONE 0x1
50
51 #define SPMI_MAX_CHANNELS 128
52 #define SPMI_MAX_SLAVES 16
53 #define SPMI_MAX_PERIPH 256
54
55 enum arb_ver {
56 V1 = 1,
57 V2,
58 V3,
59 V5 = 5
60 };
61
62 /*
63 * PMIC arbiter version 5 uses different register offsets for read/write vs
64 * observer channels.
65 */
66 enum pmic_arb_channel {
67 PMIC_ARB_CHANNEL_RW,
68 PMIC_ARB_CHANNEL_OBS,
69 };
70
71 struct msm_spmi_priv {
72 phys_addr_t arb_chnl; /* ARB channel mapping base */
73 phys_addr_t spmi_core; /* SPMI core */
74 phys_addr_t spmi_obs; /* SPMI observer */
75 /* SPMI channel map */
76 uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
77 /* SPMI bus arbiter version */
78 u32 arb_ver;
79 };
80
msm_spmi_write(struct udevice * dev,int usid,int pid,int off,uint8_t val)81 static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
82 uint8_t val)
83 {
84 struct msm_spmi_priv *priv = dev_get_priv(dev);
85 unsigned channel;
86 unsigned int ch_offset;
87 uint32_t reg = 0;
88
89 if (usid >= SPMI_MAX_SLAVES)
90 return -EIO;
91 if (pid >= SPMI_MAX_PERIPH)
92 return -EIO;
93
94 channel = priv->channel_map[usid][pid];
95
96 /* Disable IRQ mode for the current channel*/
97 writel(0x0,
98 priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
99
100 /* Write single byte */
101 writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
102
103 /* Prepare write command */
104 reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
105 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
106 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
107 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
108 reg |= 1; /* byte count */
109
110 if (priv->arb_ver == V5)
111 ch_offset = SPMI_V5_RW_CH_OFFSET(channel);
112 else
113 ch_offset = SPMI_CH_OFFSET(channel);
114
115 /* Send write command */
116 writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
117
118 /* Wait till CMD DONE status */
119 reg = 0;
120 while (!reg) {
121 reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
122 SPMI_REG_STATUS);
123 }
124
125 if (reg ^ SPMI_STATUS_DONE) {
126 printf("SPMI write failure.\n");
127 return -EIO;
128 }
129
130 return 0;
131 }
132
msm_spmi_read(struct udevice * dev,int usid,int pid,int off)133 static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
134 {
135 struct msm_spmi_priv *priv = dev_get_priv(dev);
136 unsigned channel;
137 unsigned int ch_offset;
138 uint32_t reg = 0;
139
140 if (usid >= SPMI_MAX_SLAVES)
141 return -EIO;
142 if (pid >= SPMI_MAX_PERIPH)
143 return -EIO;
144
145 channel = priv->channel_map[usid][pid];
146
147 if (priv->arb_ver == V5)
148 ch_offset = SPMI_V5_OBS_CH_OFFSET(channel);
149 else
150 ch_offset = SPMI_CH_OFFSET(channel);
151
152 /* Disable IRQ mode for the current channel*/
153 writel(0x0, priv->spmi_obs + ch_offset + SPMI_REG_CONFIG);
154
155 /* Prepare read command */
156 reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
157 reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
158 reg |= (pid << SPMI_CMD_ADDR_SHIFT);
159 reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
160 reg |= 1; /* byte count */
161
162 /* Request read */
163 writel(reg, priv->spmi_obs + ch_offset + SPMI_REG_CMD0);
164
165 /* Wait till CMD DONE status */
166 reg = 0;
167 while (!reg) {
168 reg = readl(priv->spmi_obs + ch_offset + SPMI_REG_STATUS);
169 }
170
171 if (reg ^ SPMI_STATUS_DONE) {
172 printf("SPMI read failure.\n");
173 return -EIO;
174 }
175
176 /* Read the data */
177 return readl(priv->spmi_obs + ch_offset +
178 SPMI_REG_RDATA) & 0xFF;
179 }
180
181 static struct dm_spmi_ops msm_spmi_ops = {
182 .read = msm_spmi_read,
183 .write = msm_spmi_write,
184 };
185
msm_spmi_probe(struct udevice * dev)186 static int msm_spmi_probe(struct udevice *dev)
187 {
188 struct msm_spmi_priv *priv = dev_get_priv(dev);
189 phys_addr_t config_addr;
190 u32 hw_ver;
191 u32 version;
192 int i;
193 int err;
194
195 config_addr = dev_read_addr_index(dev, 0);
196 priv->spmi_core = dev_read_addr_index(dev, 1);
197 priv->spmi_obs = dev_read_addr_index(dev, 2);
198
199 hw_ver = readl(config_addr + PMIC_ARB_VERSION);
200
201 if (hw_ver < PMIC_ARB_VERSION_V3_MIN) {
202 priv->arb_ver = V2;
203 version = 2;
204 priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
205 } else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) {
206 priv->arb_ver = V3;
207 version = 3;
208 priv->arb_chnl = config_addr + APID_MAP_OFFSET_V1_V2_V3;
209 } else {
210 priv->arb_ver = V5;
211 version = 5;
212 priv->arb_chnl = config_addr + APID_MAP_OFFSET_V5;
213
214 if (err) {
215 dev_err(dev, "could not read APID->PPID mapping table, rc= %d\n", err);
216 return -1;
217 }
218 }
219
220 dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", version, hw_ver);
221
222 if (priv->arb_chnl == FDT_ADDR_T_NONE ||
223 priv->spmi_core == FDT_ADDR_T_NONE ||
224 priv->spmi_obs == FDT_ADDR_T_NONE)
225 return -EINVAL;
226
227 dev_dbg(dev, "priv->arb_chnl address (%llu)\n", priv->arb_chnl);
228 dev_dbg(dev, "priv->spmi_core address (%llu)\n", priv->spmi_core);
229 dev_dbg(dev, "priv->spmi_obs address (%llu)\n", priv->spmi_obs);
230 /* Scan peripherals connected to each SPMI channel */
231 for (i = 0; i < SPMI_MAX_PERIPH; i++) {
232 uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
233 uint8_t slave_id = (periph & 0xf0000) >> 16;
234 uint8_t pid = (periph & 0xff00) >> 8;
235
236 priv->channel_map[slave_id][pid] = i;
237 }
238 return 0;
239 }
240
241 static const struct udevice_id msm_spmi_ids[] = {
242 { .compatible = "qcom,spmi-pmic-arb" },
243 { }
244 };
245
246 U_BOOT_DRIVER(msm_spmi) = {
247 .name = "msm_spmi",
248 .id = UCLASS_SPMI,
249 .of_match = msm_spmi_ids,
250 .ops = &msm_spmi_ops,
251 .probe = msm_spmi_probe,
252 .priv_auto = sizeof(struct msm_spmi_priv),
253 };
254