1 /*
2  * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
8 #define PLATFORM_LINKER_ARCH		aarch64
9 
10 #define PLATFORM_STACK_SIZE		0x800
11 #define CACHE_WRITEBACK_GRANULE		64
12 
13 #define PLAT_PRIMARY_CPU		U(0x0)
14 #define PLATFORM_MAX_CPU_PER_CLUSTER	U(4)
15 #define PLATFORM_CLUSTER_COUNT		U(1)
16 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
17 #define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
18 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
19 
20 #define IMX_PWR_LVL0			MPIDR_AFFLVL0
21 #define IMX_PWR_LVL1			MPIDR_AFFLVL1
22 #define IMX_PWR_LVL2			MPIDR_AFFLVL2
23 
24 #define PWR_DOMAIN_AT_MAX_LVL		U(1)
25 #define PLAT_MAX_PWR_LVL		U(2)
26 #define PLAT_MAX_OFF_STATE		U(4)
27 #define PLAT_MAX_RET_STATE		U(1)
28 
29 #define PLAT_WAIT_RET_STATE		PLAT_MAX_RET_STATE
30 #define PLAT_WAIT_OFF_STATE		U(2)
31 #define PLAT_STOP_OFF_STATE		U(3)
32 
33 #define BL31_BASE			U(0x910000)
34 #define BL31_LIMIT			U(0x920000)
35 
36 /* non-secure uboot base */
37 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
38 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
39 
40 /* GICv3 base address */
41 #define PLAT_GICD_BASE			U(0x38800000)
42 #define PLAT_GICR_BASE			U(0x38880000)
43 
44 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
45 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
46 
47 #ifdef SPD_trusty
48 #define MAX_XLAT_TABLES			5
49 #define MAX_MMAP_REGIONS		15
50 #else
51 #define MAX_XLAT_TABLES			4
52 #define MAX_MMAP_REGIONS		14
53 #endif
54 
55 #define HAB_RVT_BASE			U(0x00000880) /* HAB_RVT for i.MX8MQ */
56 
57 #define IMX_BOOT_UART_BASE		U(0x30860000)
58 #define IMX_BOOT_UART_CLK_IN_HZ		25000000 /* Select 25Mhz oscillator */
59 #define PLAT_CRASH_UART_BASE		IMX_BOOT_UART_BASE
60 #define PLAT_CRASH_UART_CLK_IN_HZ	25000000
61 #define IMX_CONSOLE_BAUDRATE		115200
62 
63 #define IMX_AIPS_BASE			U(0x30200000)
64 #define IMX_AIPS_SIZE			U(0xC00000)
65 #define IMX_AIPS1_BASE			U(0x30200000)
66 #define IMX_AIPS3_ARB_BASE		U(0x30800000)
67 #define IMX_OCOTP_BASE			U(0x30350000)
68 #define IMX_ANAMIX_BASE			U(0x30360000)
69 #define IMX_CCM_BASE			U(0x30380000)
70 #define IMX_SRC_BASE			U(0x30390000)
71 #define IMX_GPC_BASE			U(0x303a0000)
72 #define IMX_RDC_BASE			U(0x303d0000)
73 #define IMX_CSU_BASE			U(0x303e0000)
74 #define IMX_WDOG_BASE			U(0x30280000)
75 #define IMX_SNVS_BASE			U(0x30370000)
76 #define IMX_NOC_BASE			U(0x32700000)
77 #define IMX_TZASC_BASE			U(0x32F80000)
78 #define IMX_CAAM_BASE			U(0x30900000)
79 #define IMX_IOMUX_GPR_BASE		U(0x30340000)
80 #define IMX_DDRC_BASE			U(0x3d400000)
81 #define IMX_DDRPHY_BASE			U(0x3c000000)
82 #define IMX_DDR_IPS_BASE		U(0x3d000000)
83 
84 #define IMX_ROM_BASE			U(0x00000000)
85 #define IMX_ROM_SIZE			U(0x20000)
86 
87 #define AIPSTZ1_BASE			U(0x301f0000)
88 #define AIPSTZ2_BASE			U(0x305f0000)
89 #define AIPSTZ3_BASE			U(0x309f0000)
90 #define AIPSTZ4_BASE			U(0x32df0000)
91 
92 #define GPV_BASE			U(0x32000000)
93 #define GPV_SIZE			U(0x800000)
94 #define IMX_GIC_BASE			PLAT_GICD_BASE
95 #define IMX_GIC_SIZE			U(0x200000)
96 
97 #define WDOG_WSR			U(0x2)
98 #define WDOG_WCR_WDZST			BIT(0)
99 #define WDOG_WCR_WDBG			BIT(1)
100 #define WDOG_WCR_WDE			BIT(2)
101 #define WDOG_WCR_WDT			BIT(3)
102 #define WDOG_WCR_SRS			BIT(4)
103 #define WDOG_WCR_WDA			BIT(5)
104 #define WDOG_WCR_SRE			BIT(6)
105 #define WDOG_WCR_WDW			BIT(7)
106 
107 #define SRC_A53RCR0			U(0x4)
108 #define SRC_A53RCR1			U(0x8)
109 #define SRC_OTG1PHY_SCR			U(0x20)
110 #define SRC_OTG2PHY_SCR			U(0x24)
111 #define SRC_GPR1_OFFSET			U(0x74)
112 #define SRC_GPR10_OFFSET		U(0x98)
113 #define SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
114 
115 #define SNVS_LPCR			U(0x38)
116 #define SNVS_LPCR_SRTC_ENV		BIT(0)
117 #define SNVS_LPCR_DP_EN			BIT(5)
118 #define SNVS_LPCR_TOP			BIT(6)
119 
120 
121 #define IOMUXC_GPR10			U(0x28)
122 #define GPR_TZASC_EN			BIT(0)
123 #define GPR_TZASC_EN_LOCK		BIT(16)
124 
125 #define OCRAM_S_BASE			U(0x00180000)
126 #define OCRAM_S_SIZE			U(0x8000)
127 #define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
128 
129 #define COUNTER_FREQUENCY		8333333 /* 25MHz / 3 */
130 
131 #define DEBUG_CONSOLE			0
132 #define IMX_WDOG_B_RESET
133