1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * SPDX-FileCopyrightText: Copyright TF-RMM Contributors. 4 * SPDX-FileCopyrightText: Copyright Arm Limited and Contributors. 5 */ 6 7 /* This file is derived from xlat_table_v2 library in TF-A project */ 8 9 #ifndef XLAT_DEFS_PRIVATE_H 10 #define XLAT_DEFS_PRIVATE_H 11 12 #include <arch.h> 13 #include <utils_def.h> 14 #include <xlat_defs.h> 15 16 /* Miscellaneous MMU related constants */ 17 #define NUM_2MB_IN_GB (UL(1) << 9) 18 #define NUM_4K_IN_2MB (UL(1) << 9) 19 #define NUM_GB_IN_4GB (UL(1) << 2) 20 21 #define TWO_MB_SHIFT UL(21) 22 #define ONE_GB_SHIFT UL(30) 23 #define FOUR_KB_SHIFT UL(12) 24 25 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 26 #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 27 #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 28 29 /* 30 * A block descriptor points to a region of memory bigger than the granule size 31 * (e.g. a 2MB region when the granule size is 4KB). 32 */ 33 #define BLOCK_DESC UL(0x1) /* Table levels 0-2 */ 34 /* A table descriptor points to the next level of translation table. */ 35 #define TABLE_DESC UL(0x3) /* Table levels 0-2 */ 36 /* 37 * A page descriptor points to a page, i.e. a memory region whose size is the 38 * translation granule size (e.g. 4KB). 39 */ 40 #define PAGE_DESC UL(0x3) /* Table level 3 */ 41 42 #define DESC_MASK UL(0x3) 43 44 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 45 #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 46 #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 47 48 #define XN (ULL(1) << 2) 49 #define UXN (ULL(1) << 2) 50 #define PXN (ULL(1) << 1) 51 #define CONT_HINT (ULL(1) << 0) 52 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) 53 54 #define NON_GLOBAL (UL(1) << 9) 55 #define ACCESS_FLAG (UL(1) << 8) 56 #define NSH (UL(0x0) << 6) 57 #define OSH (UL(0x2) << 6) 58 #define ISH (UL(0x3) << 6) 59 60 /* Guarded Page bit */ 61 #define GP (ULL(1) << 50) 62 63 #define TABLE_ADDR_MASK XLAT_TTE_L3_PA_MASK 64 65 #define AP2_SHIFT UL(0x7) 66 #define AP2_RO ULL(0x1) 67 #define AP2_RW ULL(0x0) 68 69 #define AP1_SHIFT UL(0x6) 70 71 /* 72 * The following definitions must all be passed to the LOWER_ATTRS() macro to 73 * get the right bitmask. 74 */ 75 #define AP_RO (AP2_RO << UL(5)) 76 #define AP_RW (AP2_RW << UL(5)) 77 #define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << UL(4)) 78 #define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << UL(4)) 79 #define NS (U(0x1) << UL(3)) /* Bit[5] absolutely */ 80 #define ATTR_NON_CACHEABLE_INDEX UL(0x2) 81 #define ATTR_DEVICE_INDEX UL(0x1) 82 #define ATTR_IWBWA_OWBWA_NTR_INDEX UL(0x0) 83 #define NG_HINT (ULL(1) << 9) 84 #define LOWER_ATTRS(x) (((x) & UL(0xfff)) << UL(2)) 85 86 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ 87 #define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC) 88 /* Device-nGnRE */ 89 #define ATTR_DEVICE MAIR_DEV_NGNRE 90 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ 91 #define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA) 92 #define MAIR_ATTR_SET(attr, index) ((attr) << (index << UL(3))) 93 #define ATTR_INDEX_MASK U(0x3) 94 #define ATTR_INDEX_GET(attr) (((attr) >> UL(2)) & ATTR_INDEX_MASK) 95 96 /* 97 * Shift values for the attributes fields in a block or page descriptor. 98 * See section D4.3.3 in the ARMv8-A ARM (issue B.a). 99 */ 100 101 /* Memory attributes index field, AttrIndx[2:0]. */ 102 #define ATTR_INDEX_SHIFT 2 103 /* Non-secure bit, NS. */ 104 #define NS_SHIFT 5 105 /* Shareability field, SH[1:0] */ 106 #define SHAREABILITY_SHIFT 8 107 /* The Access Flag, AF. */ 108 #define ACCESS_FLAG_SHIFT 10 109 /* The not global bit, nG. */ 110 #define NOT_GLOBAL_SHIFT 11 111 /* Non-secure extension bit. Only valid in the EL3 translation regime */ 112 /* Contiguous hint bit. */ 113 #define CONT_HINT_SHIFT 52 114 /* Execute-never bits, XN. */ 115 #define PXN_SHIFT 53 116 #define XN_SHIFT 54 117 #define UXN_SHIFT XN_SHIFT 118 119 #endif /* XLAT_DEFS_PRIVATE_H */ 120