1 /* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7 #pragma once 8 9 #include <config.h> 10 #include <sel4/sel4_arch/constants.h> 11 12 #define PAGE_BITS seL4_PageBits 13 14 #define PPTR_VECTOR_TABLE 0xffff0000 15 16 /* Control register fields */ 17 #define CONTROL_M 0 /* MMU enable */ 18 #define CONTROL_A 1 /* Alignment fault enable */ 19 #define CONTROL_C 2 /* L1 data cache enable */ 20 #define CONTROL_W 3 /* Write buffer enable */ 21 #define CONTROL_B 7 /* Big endian mode */ 22 #define CONTROL_S 8 /* System protection (deprecated) */ 23 #define CONTROL_R 9 /* ROM protection (deprecated) */ 24 #define CONTROL_Z 11 /* Flow prediction enable */ 25 #define CONTROL_I 12 /* L1 instruction cache enable */ 26 #define CONTROL_V 13 /* Exception vector remap */ 27 #define CONTROL_RR 14 /* Cache replacement strategy */ 28 #define CONTROL_FI 21 /* Fast Interrupt enable */ 29 #define CONTROL_U 22 /* Unaligned access enable */ 30 #define CONTROL_XP 23 /* Subpage AP bits disable */ 31 #define CONTROL_VE 24 /* Vectored interrupt enable */ 32 #define CONTROL_EE 25 /* Exception E bit */ 33 #define CONTROL_TRE 28 /* TEX remap enable */ 34 #define CONTROL_AP 29 /* Access Flag Enable */ 35 36 #ifdef CONFIG_PLAT_HIKEY 37 /* Prefetcher register fields */ 38 #ifdef CONFIG_DEBUG_DISABLE_PREFETCHERS 39 40 #define PREFETCHER 0x0 41 #define PREFETCHER_MASK 0xE000 42 43 #else /* CONFIG_DEBUG_DISABLE_PREFETCHERS */ 44 45 #define L1PCTL (CONFIG_ARM_HIKEY_OUTSTANDING_PREFETCHERS << 13) /* Number of outstanding prefetch streams */ 46 #define STRIDE ((CONFIG_ARM_HIKEY_PREFETCHER_STRIDE-2) << 17) /* Consecutive strides to trigger prefetch */ 47 #define NPFSTRM ((CONFIG_ARM_HIKEY_PREFETCHER_NPFSTRM-1) << 19) /* Number of independent prefetch streams*/ 48 49 #ifndef CONFIG_ARM_HIKEY_PREFETCHER_STBPFDIS /* Disable prefetch streams from STB access */ 50 #define STBPFDIS (1 << 22) 51 #else 52 #define STBPFDIS (0 << 22) 53 #endif 54 55 #ifdef CONFIG_ARM_HIKEY_PREFETCHER_STBPFRS /* ReadUnique or ReadShared to initiate prefetch from STB access*/ 56 #define STBPFRS (1 << 23) 57 #else 58 #define STBPFRS (0 << 23) 59 #endif 60 61 #define PREFETCHER (L1PCTL | \ 62 STRIDE | \ 63 NPFSTRM | \ 64 STBPFDIS| \ 65 STBPFRS) 66 #define PREFETCHER_MASK 0xDAE000 /* Mask bits */ 67 #endif /* CONFIG_DEBUG_DISABLE_PREFETCHERS */ 68 #endif /* CONFIG_PLAT_HIKEY */ 69 70 /* Processor mode encodings (for CPS etc.) */ 71 #define PMODE_USER 0x10 72 #define PMODE_FIQ 0x11 73 #define PMODE_IRQ 0x12 74 #define PMODE_SUPERVISOR 0x13 75 #define PMODE_ABORT 0x17 76 #define PMODE_HYPERVISOR 0x1a 77 #define PMODE_UNDEFINED 0x1b 78 #define PMODE_SYSTEM 0x1f 79 /* Processor exception mask bits */ 80 #define PMASK_ASYNC_ABORT (1 << 8) 81 #define PMASK_IRQ (1 << 7) 82 #define PMASK_FIRQ (1 << 6) 83 84 /* Kernel operating mode */ 85 #ifdef CONFIG_ARM_HYPERVISOR_SUPPORT 86 #define PMODE_KERNEL PMODE_HYPERVISOR 87 #define PMODE_IDLE PMODE_HYPERVISOR 88 #else 89 #define PMODE_KERNEL PMODE_SUPERVISOR 90 #define PMODE_IDLE PMODE_SYSTEM 91 #endif 92 93 #ifndef __ASSEMBLER__ 94 95 #include <arch/types.h> 96 97 enum vm_page_size { 98 ARMSmallPage, 99 ARMLargePage, 100 ARMSection, 101 ARMSuperSection 102 }; 103 typedef word_t vm_page_size_t; 104 105 enum frameSizeConstants { 106 ARMSmallPageBits = seL4_PageBits, 107 ARMLargePageBits = seL4_LargePageBits, 108 ARMSectionBits = seL4_SectionBits, 109 ARMSuperSectionBits = seL4_SuperSectionBits 110 }; 111 pageBitsForSize(vm_page_size_t pagesize)112static inline word_t CONST pageBitsForSize(vm_page_size_t pagesize) 113 { 114 switch (pagesize) { 115 case ARMSmallPage: 116 return ARMSmallPageBits; 117 118 case ARMLargePage: 119 return ARMLargePageBits; 120 121 case ARMSection: 122 return ARMSectionBits; 123 124 case ARMSuperSection: 125 return ARMSuperSectionBits; 126 127 default: 128 fail("Invalid page size"); 129 } 130 } 131 132 #endif /* __ASSEMBLER__ */ 133 134