1 /**
2 ******************************************************************************
3 * @file rl6548.c
4 * @author
5 * @version V1.0.0
6 * @date 2018-12-12
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Audio codec peripheral:
9 * - Codec Initialization
10 * - Codec parameters configuration
11 * - SI read/write configuration
12 * - SI Clock configuration
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * This module is a confidential and proprietary property of RealTek and
18 * possession or use of this module requires written permission of RealTek.
19 *
20 * Copyright(c) 2018, Realtek Semiconductor Corporation. All rights reserved.
21 ******************************************************************************
22 */
23 #include "ameba_soc.h"
24 #include "rl6548.h"
25 #include "rl6548_eq_table.h"
26 /**
27 * @brief Enables or disables the specified AUDIO SI peripheral.
28 * @param new_state: new state of the SIx peripheral.
29 * This parameter can be: ENABLE or DISABLE.
30 * @retval None
31 */
AUDIO_SI_Cmd(u8 new_state)32 void AUDIO_SI_Cmd(u8 new_state)
33 {
34 AUDIO_SI_TypeDef* SIx = AUDIO_SI_DEV;
35
36 if (new_state == ENABLE) {
37 SIx->SI_CTRLR &= ~ BIT_CTRLR_SI_DISABLE;
38 } else {
39 SIx->SI_CTRLR |= BIT_CTRLR_SI_DISABLE;
40 }
41 }
42
43 /**
44 * @brief SI write codec register.
45 * @param address: codec register address.
46 * @param data: data which write to register.
47 * @retval None
48 */
AUDIO_SI_WriteReg(u32 address,u32 data)49 void AUDIO_SI_WriteReg(u32 address, u32 data)
50 {
51 u32 cnt = 0;
52 AUDIO_SI_TypeDef* SIx = AUDIO_SI_DEV;
53
54 SIx->SI_CTRLR = (address << 8) | (data << 16) | BIT_CTRLR_SI_WR_START;
55
56 while((SIx->SI_CTRLR & BIT_CTRLR_SI_WR_START) && (++cnt) < 100000);
57
58 if (cnt == 100000){
59 DBG_8195A("write codec reg fail!!\n");
60 }
61 }
62
63 /**
64 * @brief SI read codec register.
65 * @param address: codec register address.
66 * @retval value of register.
67 */
AUDIO_SI_ReadReg(u32 address)68 u16 AUDIO_SI_ReadReg(u32 address)
69 {
70 u32 reg_value = 0;
71 u32 cnt = 0;
72 AUDIO_SI_TypeDef* SIx = AUDIO_SI_DEV;
73
74 /* Configure Read command */
75 SIx->SI_CTRLR = (address << 8) | BIT_CTRLR_SI_RD_START;
76
77 do {
78 reg_value = SIx->SI_CTRLR;
79 /* waiting for read done */
80 } while((reg_value & BIT_CTRLR_SI_RD_START) && (++cnt) < 100000);
81
82 if (cnt == 100000){
83 DBG_8195A("read codec reg fail!!\n");
84 return 0;
85 }
86
87 return ((reg_value & BIT_CTRLR_SI_DATA) >> 16);
88 }
89
90 /**
91 * @brief Turn on or turn off the clock of register bank of audio codec.
92 * @param new_state: new state of the clock of register bank of audio codec.
93 * This parameter can be: ENABLE or DISABLE.
94 * @retval None
95 */
AUDIO_SI_ClkCmd(u8 new_state)96 void AUDIO_SI_ClkCmd(u8 new_state)
97 {
98 AUDIO_SI_TypeDef* SIx = AUDIO_SI_DEV;
99
100 if (new_state == ENABLE) {
101 SIx->SI_CLK_EN |= BIT_SI_CLK_EN;
102 } else {
103 SIx->SI_CLK_EN &= ~ BIT_SI_CLK_EN;
104 }
105 }
106
107 /**
108 * @brief Initialize codec peripheral.
109 * @param sample_rate: codec ADC and DAC sample rate.
110 * This parameter can be one of the following values:
111 * @arg SR_8K: sample rate is 8kHz
112 * @arg SR_16K: sample rate is 16kHz
113 * @arg SR_32K: sample rate is 32kHz
114 * @arg SR_48K: sample rate is 48kHz
115 * @arg SR_96K: sample rate is 96kHz
116 * @arg SR_44P1K: sample rate is 44.1kHz
117 * @arg SR_88P2K: sample rate is 88.2kHz
118 * @param word_len: data sample bit
119 * This parameter can be one of the following values:
120 * @arg WL_16: sample bit is 16 bit
121 * @arg WL_24: sample bit is 24 bit
122 * @arg WL_8: sample bit is 8 bit
123 * @param mono_stereo: mono channel or stereo channel
124 * This parameter can be one of the following values:
125 * @arg CH_STEREO: stereo channel, channel number is 2
126 * @arg CH_MONO: mono channel, channel number is 1
127 * @param application: application mode
128 * This parameter can be one of the following values:
129 * @arg APP_AMIC_IN: analog microphone in
130 * @arg APP_DMIC_IN: digital microphone in
131 * @arg APP_LINE_IN: line in
132 * @arg APP_LINE_OUT: line out
133 * @arg APP_DAAD_LPBK: loopback
134 * @return None
135 */
CODEC_Init(u32 sample_rate,u32 word_len,u32 mono_stereo,u32 application)136 void CODEC_Init(u32 sample_rate, u32 word_len, u32 mono_stereo, u32 application)
137 {
138 uint32_t reg_value = 0, reg_value2 = 0, reg_value3 = 0;
139
140 reg_value = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL);
141 reg_value &= ~(BIT_LSYS_MASK_AC_LDO_REG << BIT_LSYS_SHIFT_AC_LDO_REG);
142 //restore the pad power
143 if (is_power_supply18()){
144 reg_value |= ((u32)0x68) << BIT_LSYS_SHIFT_AC_LDO_REG;
145 }
146 else{
147 reg_value |= ((u32)0x2A) << BIT_LSYS_SHIFT_AC_LDO_REG;
148 }
149 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, reg_value);
150
151 /* ================= CODEC initialize ======================== */
152
153 if ((application&APP_DAAD_LPBK) == APP_DAAD_LPBK){
154 reg_value3 = (1<<BIT_ADC_L_AD_ZDET_TOUT | 1<<BIT_ADC_L_AD_ZDET_FUNC | 2<<BIT_ADC_L_ADJ_HPF_COEF_SEL);
155 AUDIO_SI_WriteReg(ADC_L_CTRL, reg_value3);
156 reg_value3 = 0;
157
158 reg_value3 = (1<<BIT_ADC_R_AD_ZDET_TOUT | 1<<BIT_ADC_R_AD_ZDET_FUNC | 2<<BIT_ADC_R_ADJ_HPF_COEF_SEL);
159 AUDIO_SI_WriteReg(ADC_R_ADJ_D, reg_value3);
160 reg_value3 = 0;
161
162 reg_value = AUDIO_SI_ReadReg(ASRC_CTRL);
163 reg_value |= (1 | 1<<BIT_ASRC_FTK_LOOP_EN | 1<<BIT_ASRC_256FS_SYS_SEL);
164 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value);
165
166 reg_value = AUDIO_SI_ReadReg(ASRC_CTRL);
167 reg_value |= (1 << BIT_ASRC_EN);
168 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value);
169
170 reg_value3 = (1<<BIT_DA_L_EN | 1<<BIT_DA_R_EN | 1<<BIT_MOD_L_EN | 1<<BIT_MOD_R_EN | 1<<BIT_DA_ANA_CLK_EN | 1<<BIT_DA_FIFO_EN\
171 | 1<<BIT_AD_L_EN | 1<<BIT_AD_R_EN | 1<<BIT_AD_FIFO_EN | 1<<BIT_AD_ANA_CLK_EN | 1<<BIT_AD_ANA_L_EN | 1<<BIT_AD_ANA_R_EN);
172 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL,reg_value3);
173 reg_value3 = 0;
174
175 reg_value = AUDIO_SI_ReadReg(DAC_L_MUTE_CTRL);
176 reg_value |= (1<<BIT_DAAD_LPBK_EN);
177 AUDIO_SI_WriteReg(DAC_L_MUTE_CTRL, reg_value);
178
179 reg_value = AUDIO_SI_ReadReg(ADC_DMIC_L_FILTER_CTRL);
180 reg_value &= (0xffff&(~(1<<BIT_ADC_L_DMIC_MIX_MUTE)));
181 reg_value |= (1<<BIT_ADC_L_AD_MIX_MUTE);
182 AUDIO_SI_WriteReg(ADC_DMIC_L_FILTER_CTRL, reg_value);
183
184 reg_value = AUDIO_SI_ReadReg(ADC_DMIC_R_FILTER_CTRL);
185 reg_value &= (0xffff&(~(1<<BIT_ADC_R_DMIC_MIX_MUTE)));
186 reg_value |= (1<<BIT_ADC_R_AD_MIX_MUTE);
187 AUDIO_SI_WriteReg(ADC_DMIC_R_FILTER_CTRL, reg_value);
188
189
190 reg_value = AUDIO_SI_ReadReg(DAC_ADC_MIC_CLK_CTRL);
191 reg_value |= (1<<BIT_DMIC_L_EN | 1<<BIT_DMIC_R_EN | 1<<BIT_DMIC_CLK_EN);
192 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL, reg_value);
193
194 reg_value3 = (1 | 1<<BIT_ASRC_FTK_LOOP_EN | 1<<BIT_ASRC_256FS_SYS_SEL | 1<<BIT_ASRC_EN);
195 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value3);
196 reg_value3 = 0;
197
198 AUDIO_SI_WriteReg(DAC_ADC_SR_CTRL, (sample_rate << 4) | sample_rate);
199
200 reg_value3 = (1<<BIT_I2S_RST_N_REG);
201 AUDIO_SI_WriteReg(I2S_CTRL, reg_value3);
202 reg_value3 = 0;
203 return;
204 }
205
206 reg_value = AUDIO_SI_ReadReg(MICBST_CTRL); //VREF voltage selection
207 reg_value &= (0xffff&(~(3<<BIT_VREF_VREFSEL)));
208 reg_value |= (2<<BIT_VREF_VREFSEL);
209 AUDIO_SI_WriteReg(MICBST_CTRL, reg_value);
210
211 if ((application&APP_LINE_OUT) == APP_LINE_OUT){
212 reg_value = AUDIO_SI_ReadReg(DAC_ADC_MIC_CLK_CTRL); //dac modulation/filter/fifo on
213 reg_value |= (1<<BIT_DA_L_EN | 1<<BIT_DA_R_EN | 1<<BIT_MOD_L_EN | 1<<BIT_MOD_R_EN | 1<<BIT_DA_ANA_CLK_EN | 1<<BIT_DA_FIFO_EN);
214 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL, reg_value);
215
216 //step1
217 reg_value = AUDIO_SI_ReadReg(GEN_CTRL);
218 reg_value &= (1<<BIT_DTSDM_POW_L | 1<<BIT_DTSDM_POW_R);
219 reg_value |= (1<<BIT_DAC_ADDACK_POW | 1<<BIT_DAC_CKXEN | 1<<BIT_DAC_L_POW | 1<<BIT_DAC_R_POW | 1<<BIT_DPRAMP_POW | 1<<BIT_DTSDM_CKXEN);
220 AUDIO_SI_WriteReg(GEN_CTRL, reg_value);
221
222 reg_value3 = (3<<BIT_HPO_DPRSELL | 3<<BIT_HPO_DPRSELR | 1<< BIT_HPO_ENAL | 1<< BIT_HPO_ENAR |\
223 1<<BIT_HPO_ENDPL | 1<<BIT_HPO_ENDPR | 1<<BIT_HPO_L_POW);
224 AUDIO_SI_WriteReg(HPO_CTRL, reg_value3);
225 reg_value3 = 0;
226
227 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL);
228 reg_value &= (1<<BIT_MICBIAS_POW | 3<<BIT_MICBIAS_VSET);
229 reg_value |= (2<<BIT_HPO_ML | 2 <<BIT_HPO_MR | 1<<BIT_HPO_R_POW | 1<<BIT_HPO_SEL | 1<<BIT_HPO_SER | 1<<BIT_MBIAS_POW | 1<<BIT_VREF_POW);
230 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
231
232 reg_value3 = (1<<BIT_CKX_MICBIAS_EN);
233 AUDIO_SI_WriteReg(CK_DEPOP_MICBIAS, reg_value3);
234 reg_value3 = 0;
235
236 //step2
237 reg_value3 = (0xffff & (~(1<<BIT_HPO_CLPDPR | 1<<BIT_HPO_CLR | 1<<BIT_HPO_OPNDPL | 1<<BIT_HPO_OPNDPR)));
238 AUDIO_SI_WriteReg(HPO_CTRL, reg_value3);
239 reg_value3 = 0;
240
241 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL);
242 reg_value &= (1<<BIT_MICBIAS_POW | 3<<BIT_MICBIAS_VSET);
243 reg_value |= (2<<BIT_HPO_ML | 2<<BIT_HPO_MR | 1<<BIT_HPO_OPPDPR | 1<<BIT_HPO_R_POW | 1<<BIT_HPO_SEL | 1<<BIT_HPO_SER | 1<<BIT_MBIAS_POW | 1<<BIT_VREF_POW);
244 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
245
246 //step3
247 reg_value = AUDIO_SI_ReadReg(GEN_CTRL);
248 reg_value &= (1<<BIT_DTSDM_POW_L | 1<<BIT_DTSDM_POW_R);
249 reg_value |= (1<<BIT_DAC_ADDACK_POW | 1<<BIT_DAC_CKXEN | 1<<BIT_DAC_L_POW | 1<<BIT_DAC_R_POW | 1<<BIT_DPRAMP_ENRAMP | 1<<BIT_DPRAMP_POW | 1<<BIT_DTSDM_CKXEN);
250 AUDIO_SI_WriteReg(GEN_CTRL, reg_value);
251
252 reg_value3 = (1<<BIT_BB_CK_DEPOP_EN | 1<<BIT_CKX_MICBIAS_EN);
253 AUDIO_SI_WriteReg(CK_DEPOP_MICBIAS, reg_value3);
254 reg_value3 = 0;
255 }
256
257 if (((application&APP_AMIC_IN) == APP_AMIC_IN) || ((application&APP_LINE_IN) == APP_LINE_IN)){
258 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL); //vref power on
259 reg_value &= (0xffff & (~(1<<BIT_MICBST_ENDFL | 1<<BIT_MICBST_ENDFR )));
260 reg_value |= (1<<BIT_MBIAS_POW | 1<<BIT_VREF_POW);
261 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
262
263 DelayUs(5);
264
265 if ((application&APP_AMIC_IN) == APP_AMIC_IN){
266 reg_value = AUDIO_SI_ReadReg(CK_DEPOP_MICBIAS); //micbias chopper clock enable
267 reg_value |= (1<<BIT_CKX_MICBIAS_EN);
268 AUDIO_SI_WriteReg(CK_DEPOP_MICBIAS, reg_value);
269
270 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL); //release micbias chopper clock gate and mic_bias on
271 reg_value |= (1<<BIT_MICBIAS_ENCHX | 1<<BIT_MICBIAS_POW);
272 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
273 DelayUs(100);
274
275 reg_value = AUDIO_SI_ReadReg(MICBST_CTRL); //PGA on and unmute mic
276 reg_value &= (0xffff & (~(3<<BIT_MICBST_MUTE_L | 3<<BIT_MICBST_MUTE_R)));
277 reg_value |= (2<<BIT_MICBST_MUTE_L | 2<<BIT_MICBST_MUTE_R | 3<<BIT_MICBST_POW);
278 AUDIO_SI_WriteReg(MICBST_CTRL, reg_value);
279 }
280 else{
281 reg_value = AUDIO_SI_ReadReg(MICBST_CTRL); //PGA on and unmute line-in
282 reg_value &= (0xffff & (~(3<<BIT_MICBST_GSELL | 3<<BIT_MICBST_GSELR | 3<<BIT_MICBST_MUTE_L | 3<<BIT_MICBST_MUTE_R)));
283 reg_value |= (1<<BIT_MICBST_MUTE_L | 1<<BIT_MICBST_MUTE_R | 3<<BIT_MICBST_POW);
284 AUDIO_SI_WriteReg(MICBST_CTRL, reg_value);
285 }
286 }
287
288 if (((application&APP_AMIC_IN) == APP_AMIC_IN) || ((application&APP_LINE_IN) == APP_LINE_IN) || ((application&APP_LINE_OUT) == APP_LINE_OUT)) {
289 DelayMs(200);
290 }
291
292 if ((application&APP_LINE_OUT) == APP_LINE_OUT){
293 //step5
294 reg_value = AUDIO_SI_ReadReg(GEN_CTRL);
295 reg_value &= (1<<BIT_DTSDM_POW_L | 1<<BIT_DTSDM_POW_R);
296 reg_value |= (1<<BIT_DAC_ADDACK_POW | 1<<BIT_DAC_CKXEN | 1<<BIT_DAC_L_POW | 1<<BIT_DAC_R_POW | 1<<BIT_DTSDM_CKXEN);
297 AUDIO_SI_WriteReg(GEN_CTRL, reg_value);
298
299 reg_value3 = (3<<BIT_HPO_DPRSELL | 3<<BIT_HPO_DPRSELR | 3<<BIT_HPO_ENAL | 1<<BIT_HPO_L_POW);
300 AUDIO_SI_WriteReg(HPO_CTRL, reg_value3);
301 reg_value3 = 0;
302
303 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL);
304 reg_value &= (1<<BIT_MICBIAS_POW | 3<<BIT_MICBIAS_VSET);
305 reg_value |= (2<<BIT_HPO_ML | 2<<BIT_HPO_MR | 2<<BIT_HPO_OPPDPR | 1<<BIT_HPO_SEL | 1<<BIT_HPO_SER | 1<<BIT_MBIAS_POW | 1<<BIT_VREF_POW);
306 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
307
308 reg_value3 = (1<<BIT_CKX_MICBIAS_EN);
309 AUDIO_SI_WriteReg(CK_DEPOP_MICBIAS, reg_value3);
310 reg_value3 = 0;
311 }
312
313 if (((application&APP_AMIC_IN) == APP_AMIC_IN) || ((application&APP_LINE_IN) == APP_LINE_IN)){
314 reg_value = AUDIO_SI_ReadReg(GEN_CTRL); //adc on
315 reg_value |= (1<<BIT_DAC_ADDACK_POW | 1<<BIT_DTSDM_CKXEN | 1<<BIT_DTSDM_POW_L | 1<<BIT_DTSDM_POW_R);
316 AUDIO_SI_WriteReg(GEN_CTRL, reg_value);
317 DelayUs(50);
318 }
319
320 /* Configure ADC and DAC corresponding clock */
321 reg_value3 = (1<<BIT_DA_L_EN | 1<<BIT_DA_R_EN | 1<<BIT_MOD_L_EN | 1<<BIT_MOD_R_EN | 1<<BIT_DA_ANA_CLK_EN | 1<<BIT_DA_FIFO_EN | 1<<BIT_AD_L_EN\
322 | 1<<BIT_AD_R_EN | 1<<BIT_AD_FIFO_EN | 1<<BIT_AD_ANA_CLK_EN | 1<<BIT_AD_ANA_L_EN | 1<<BIT_AD_ANA_R_EN);
323 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL, reg_value3);
324 reg_value3 = 0;
325 /* Left channel: Enable High pass filter enable control (filter DC), analog ADC input path mute control Left Channel */
326 /* Enable ADC SRC 1st LPF control and ADC SRC 2nd LPF control, DMIC SRC 1st LPF fc:46.92kHz */
327 reg_value3 = (1<<BIT_ADC_L_DMIC_LPF1ST_FC_SEL | 1<<BIT_ADC_L_AD_LPF2ND_EN | 1<<BIT_ADC_L_AD_LPF1ST_EN | 1<<BIT_ADC_L_DMIC_MIX_MUTE | 1<<BIT_ADC_L_AD_DCHPF_EN);
328
329 AUDIO_SI_WriteReg(ADC_DMIC_L_FILTER_CTRL, reg_value3);
330 reg_value3 = 0;
331 /* Right channel: Enable High pass filter enable control (filter DC), analog ADC input path mute control Left Channel */
332 /* Enable ADC SRC 1st LPF control and ADC SRC 2nd LPF control, DMIC SRC 1st LPF fc:46.92kHz */
333 reg_value3 = (1<<BIT_ADC_R_DMIC_LPF1ST_FC_SEL | 1<<BIT_ADC_R_AD_LPF2ND_EN | 1<<BIT_ADC_R_AD_LPF1ST_EN | 1<<BIT_ADC_R_DMIC_MIX_MUTE | 1<<BIT_ADC_R_AD_DCHPF_EN);
334 AUDIO_SI_WriteReg(ADC_DMIC_R_FILTER_CTRL, reg_value3);
335 reg_value3 = 0;
336
337 if (((application&APP_AMIC_IN) == APP_AMIC_IN) || ((application&APP_LINE_IN) == APP_LINE_IN)){
338 reg_value = AUDIO_SI_ReadReg(ADC_L_CTRL);
339 reg_value2 = AUDIO_SI_ReadReg(ADC_R_ADJ_D);
340
341 reg_value &= (0xffff&(~(7<<BIT_ADC_L_ADJ_HPF_COEF_SEL | 3<<BIT_ADC_L_AD_ZDET_FUNC)));
342 reg_value |= (1<<BIT_ADC_L_ADJ_HPF_2ND_EN);
343
344 reg_value2 &= (0xffff & (~(7<<BIT_ADC_R_ADJ_HPF_COEF_SEL | 3<<BIT_ADC_R_AD_ZDET_FUNC)));
345 reg_value2 |= (1<<BIT_ADC_R_ADJ_HPF_2ND_EN);
346
347 switch(sample_rate){
348 case SR_8K:
349 case SR_16K:
350 break;
351 case SR_32K:
352 reg_value |= (1<<BIT_ADC_L_ADJ_HPF_COEF_SEL);
353 reg_value2 |= (1<<BIT_ADC_R_ADJ_HPF_COEF_SEL);
354 break;
355 case SR_44P1K:
356 case SR_48K:
357 reg_value |= (2<<BIT_ADC_L_ADJ_HPF_COEF_SEL);
358 reg_value2 |= (2<<BIT_ADC_R_ADJ_HPF_COEF_SEL);
359 break;
360 case SR_88P2K:
361 case SR_96K:
362 reg_value |= (3<<BIT_ADC_L_ADJ_HPF_COEF_SEL);
363 reg_value2 |= (3<<BIT_ADC_R_ADJ_HPF_COEF_SEL);
364 break;
365 default:
366 break;
367 }
368
369 AUDIO_SI_WriteReg(ADC_L_CTRL, reg_value);
370 AUDIO_SI_WriteReg(ADC_R_ADJ_D, reg_value2);
371
372 DelayMs(50); //maybe need fine tune per board
373 }
374
375 reg_value3 = (1<<BIT_AUDIO_IP_TCON_EN | 1<<BIT_ASRC_FTK_LOOP_EN | 1<<BIT_ASRC_256FS_SYS_SEL | 1<<BIT_ASRC_EN);
376 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value3);
377 reg_value3 = 0;
378
379 /* ADC and DAC sample rate 16K */
380 AUDIO_SI_WriteReg(DAC_ADC_SR_CTRL, (sample_rate << 4) | sample_rate);
381 /* Left channel: mon DAC Lch 128fs-domain mixer sidetone path mute enable, Digital DAC & ADC loop back control, mon DAC Lch dvol mute enable */
382 reg_value = AUDIO_SI_ReadReg(DAC_L_MUTE_CTRL);
383 //AUDIO_SI_WriteReg(0xfb, 0x4);
384 reg_value |= BIT3;
385 AUDIO_SI_WriteReg(DAC_L_MUTE_CTRL, reg_value & 0xfff9);
386 /* Right channel: mon DAC Rch 128fs-domain mixer sidetone path mute enable, Digital DAC & ADC loop back control, mon DAC Rch dvol mute enable */
387 reg_value = AUDIO_SI_ReadReg(DAC_R_MUTE_CTRL);
388 reg_value |= BIT3;
389 AUDIO_SI_WriteReg(DAC_R_MUTE_CTRL, reg_value & 0xfff9);
390 /* Enable control for dac filter; ALC is stereo mode */
391 reg_value = AUDIO_SI_ReadReg(ALC_MIN_GAIN);
392 reg_value &= (0xffff &(~(1<<BIT_DA_STEREO_MODE_EN)));
393
394 if (mono_stereo == CH_STEREO){
395 reg_value |= BIT8;
396 }
397 AUDIO_SI_WriteReg(ALC_MIN_GAIN, reg_value);
398 reg_value = AUDIO_SI_ReadReg(DAC_L_CTRL);
399 reg_value &= (0xff<<BIT_DAC_L_DA_GAIN | 1<<BIT_DAC_L_DAHPF_EN | 2<<BIT_DAC_L_DA_DITHER_SEL);
400 reg_value |= (2 << BIT_DAC_L_DA_ZDET_FUNC);
401
402 AUDIO_SI_WriteReg(DAC_L_CTRL, reg_value);
403 AUDIO_SI_WriteReg(DAC_R_CTRL, reg_value);
404
405
406 if ((application&APP_DMIC_IN) == APP_DMIC_IN){
407 reg_value = AUDIO_SI_ReadReg(ADC_DMIC_L_FILTER_CTRL);
408 reg_value &= (0xffff & (~(1<<BIT_ADC_L_DMIC_RI_FA_SEL | 1<<BIT_ADC_L_DMIC_MIX_MUTE)));
409 reg_value |= (1<<BIT_ADC_L_DMIC_RI_FA_SEL | 1<<BIT_ADC_L_DMIC_LPF2ND_EN | 1<<BIT_ADC_L_DMIC_LPF1ST_EN | 1<<BIT_ADC_L_AD_MIX_MUTE | 1<<BIT_ADC_L_AD_DCHPF_EN);
410 AUDIO_SI_WriteReg(ADC_DMIC_L_FILTER_CTRL, reg_value);
411
412 reg_value = AUDIO_SI_ReadReg(ADC_L_CTRL);
413 reg_value |= (1<<BIT_ADC_L_ADJ_HPF_2ND_EN);
414 AUDIO_SI_WriteReg(ADC_L_CTRL, reg_value);
415
416 reg_value = AUDIO_SI_ReadReg(ADC_DMIC_R_FILTER_CTRL);
417 reg_value &= (0xffff & (~(1<<BIT_ADC_R_DMIC_RI_FA_SEL | 1<<BIT_ADC_R_DMIC_MIX_MUTE)));
418 reg_value |= (1<<BIT_ADC_L_DMIC_LPF2ND_EN | 1<<BIT_ADC_L_DMIC_LPF1ST_EN | 1<<BIT_ADC_L_AD_MIX_MUTE | 1<<BIT_ADC_L_AD_DCHPF_EN);
419 AUDIO_SI_WriteReg(ADC_DMIC_R_FILTER_CTRL, reg_value); //bit0: 0 means latching rising edge, whereas 1 means falling edge.
420
421 reg_value = AUDIO_SI_ReadReg(ADC_R_ADJ_D);
422 reg_value |= (1<<BIT_ADC_R_ADJ_HPF_2ND_EN);
423 AUDIO_SI_WriteReg(ADC_R_ADJ_D, reg_value);
424
425 reg_value = AUDIO_SI_ReadReg(DAC_ADC_SR_CTRL);
426 reg_value &= (0xffff&(~(7<<BIT_DMIC_CLK_SEL)));
427 reg_value |= (1<<BIT_DMIC_CLK_SEL);
428 AUDIO_SI_WriteReg(DAC_ADC_SR_CTRL, reg_value);
429
430 reg_value = AUDIO_SI_ReadReg(DAC_ADC_MIC_CLK_CTRL);
431 reg_value |= (1<<BIT_DMIC_L_EN | 1<<BIT_DMIC_R_EN | 1<<BIT_DMIC_CLK_EN);
432 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL, reg_value);
433 }
434
435 if ((sample_rate == SR_96K) || (sample_rate == SR_88P2K)){
436 reg_value = AUDIO_SI_ReadReg(DAC_ADC_SR_CTRL);
437 reg_value &= (0xffff &(~(15<<BIT_ASRC_FSI_RATE_MANUAL)));
438 reg_value |= (1<<BIT_ASRC_FSI_RATE_MANUAL);
439 AUDIO_SI_WriteReg(DAC_ADC_SR_CTRL, reg_value);
440
441 reg_value = AUDIO_SI_ReadReg(ASRC_CTRL);
442 reg_value &= (0xffff&(~(3<<BIT_ASRC_256FS_SYS_SEL)));
443 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value);
444 }
445
446 reg_value = ((word_len << 4) |mono_stereo | 0x0080);
447 AUDIO_SI_WriteReg(I2S_CTRL, reg_value);
448 }
449
450 /**
451 * @brief Set line out to differential mode.
452 * @param None
453 * @return None
454 */
CODEC_SetLineoutDifferential()455 void CODEC_SetLineoutDifferential(){
456 uint32_t reg_value = 0;
457 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL);
458 reg_value &= (0xffff&(~(1<<BIT_HPO_SEL | 1<<BIT_HPO_SER)));
459 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
460 }
461
462
463 /**
464 * @brief Set codec volume by controlling mon DAC channel dvol gain.
465 * @param vol_lch: mon DAC Lch dvol gain control(0.375dB/step)
466 * This parameter can be one of the following values:
467 * @arg 8'hAF: 0dB
468 * @arg ...
469 * @arg 8'h00: -65.625dB
470 * @param vol_rch: mon DAC Rch dvol gain control(0.375dB/step)
471 * This parameter can be one of the following values:
472 * @arg 8'hAF: 0dB
473 * @arg ...
474 * @arg 8'h00: -65.625dB
475 * @return None
476 */
CODEC_SetVolume(u8 vol_lch,u8 vol_rch)477 void CODEC_SetVolume(u8 vol_lch, u8 vol_rch)
478 {
479 u32 reg_value = 0;
480
481 reg_value = AUDIO_SI_ReadReg(DAC_L_CTRL);
482 reg_value &= ~0xff;
483 reg_value |= vol_lch;
484
485 AUDIO_SI_WriteReg(DAC_L_CTRL, reg_value);
486
487 reg_value = AUDIO_SI_ReadReg(DAC_R_CTRL);
488 reg_value &= ~0xff;
489 reg_value |= vol_rch;
490
491 AUDIO_SI_WriteReg(DAC_R_CTRL, reg_value);
492 }
493
494 /**
495 * @brief Get codec mon DAC channel gain control.
496 * @param vol: mon DAC DAC channel dvol gain
497 * @note vol value high 8 bits is rch gain, low 8 bits are lch gain
498 * @return None
499 */
CODEC_GetVolume(u16 * vol)500 void CODEC_GetVolume(u16 *vol)
501 {
502 u8 vol_lch = 0;
503 u8 vol_rch = 0;
504
505 vol_lch = AUDIO_SI_ReadReg(DAC_L_CTRL) & 0xff;
506 vol_rch = AUDIO_SI_ReadReg(DAC_R_CTRL) & 0xff;
507
508 *vol = (vol_rch << 8) | vol_lch;
509 }
510
511 /**
512 * @brief Set codec ADC and DAC sample rate.
513 * @param sample_rate: codec ADC and DAC sample rate.
514 * This parameter can be one of the following values:
515 * @arg SR_8K: sample rate is 8kHz
516 * @arg SR_16K: sample rate is 16kHz
517 * @arg SR_32K: sample rate is 32kHz
518 * @arg SR_48K: sample rate is 48kHz
519 * @arg SR_96K: sample rate is 96kHz
520 * @arg SR_44P1K: sample rate is 44.1kHz
521 * @arg SR_88P2K: sample rate is 88.2kHz
522 * @return None
523 */
CODEC_SetSr(u32 sample_rate)524 void CODEC_SetSr(u32 sample_rate){
525 u32 reg_value = 0;
526
527 if ((sample_rate == SR_96K) || (sample_rate == SR_88P2K)){
528 reg_value = AUDIO_SI_ReadReg(DAC_ADC_SR_CTRL);
529 reg_value &= (7<<BIT_DMIC_CLK_SEL | 1<<BIT_ASRC_FSI_GATING_EN);
530 reg_value |= (0x0800|(sample_rate << 4) | sample_rate);
531 AUDIO_SI_WriteReg(DAC_ADC_SR_CTRL, reg_value);
532
533 reg_value = AUDIO_SI_ReadReg(ASRC_CTRL);
534 reg_value &= (0xffff & (~(3<<BIT_ASRC_256FS_SYS_SEL)));
535 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value);
536 }
537 else{
538 reg_value = AUDIO_SI_ReadReg(DAC_ADC_SR_CTRL);
539 reg_value &= (7<<BIT_DMIC_CLK_SEL | 1<<BIT_ASRC_FSI_GATING_EN);
540 reg_value |= ((sample_rate << 4) | sample_rate);
541
542 AUDIO_SI_WriteReg(DAC_ADC_SR_CTRL, reg_value);
543
544 reg_value = AUDIO_SI_ReadReg(ASRC_CTRL);
545 reg_value &= (0xffff & (~(3<<BIT_ASRC_256FS_SYS_SEL)));
546 reg_value |=(1<<BIT_ASRC_256FS_SYS_SEL);
547 AUDIO_SI_WriteReg(ASRC_CTRL, reg_value);
548 }
549
550 }
551
552 /**
553 * @brief Set codec ADC and DAC channel number.
554 * @param mono_stereo: codec ADC and DAC channel number.
555 * This parameter can be one of the following values:
556 * @arg CH_MONO: mono
557 * @arg CH_STEREO: stereo
558 * @return None
559 */
CODEC_SetCh(u32 mono_stereo)560 void CODEC_SetCh(u32 mono_stereo){
561 u32 reg_value = 0;
562
563 reg_value = AUDIO_SI_ReadReg(I2S_CTRL);
564 reg_value &= (0xffff & ~(1<<BIT_EN_I2S_MONO));
565 reg_value |= mono_stereo;
566
567 AUDIO_SI_WriteReg(I2S_CTRL, reg_value);
568
569 reg_value = AUDIO_SI_ReadReg(ALC_MIN_GAIN);
570 reg_value &= (0xffff & ~(1<<BIT_DA_STEREO_MODE_EN));
571 if (mono_stereo == CH_STEREO){
572 reg_value |= BIT8;
573 }
574
575 AUDIO_SI_WriteReg(ALC_MIN_GAIN, reg_value);
576 }
577
578
579 /**
580 * @brief Set codec ADC gain.
581 * @param ad_gain_left: ADC left channel digital volume gain
582 * This parameter can be one of the following values:
583 * @arg 7'h00: -17.625dB
584 * @arg ...
585 * @arg 7'h2f: 0dB
586 * @arg 7'h30: 0.375dB
587 * @arg ...
588 * @arg 7'h7f: 30dB
589 * @param ad_gain_right: ADC right channel digital volume gain
590 * This parameter can be one of the following values:
591 * @arg 7'h00: -17.625dB
592 * @arg ...
593 * @arg 7'h2f: 0dB
594 * @arg 7'h30: 0.375dB
595 * @arg ...
596 * @arg 7'h7f: 30dB
597 * @note ADC digital volume is -17.625dB~+30dB in 0.375 dB step.
598 * @return None
599 */
CODEC_SetAdcGain(u32 ad_gain_left,u32 ad_gain_right)600 void CODEC_SetAdcGain(u32 ad_gain_left, u32 ad_gain_right)
601 {
602 u32 reg_value = 0;
603
604 reg_value = AUDIO_SI_ReadReg(ADC_L_GAIN);
605 reg_value &= ~(0x7f<<ADC_L_AD_GAIN);
606 reg_value |= (ad_gain_left << ADC_L_AD_GAIN);
607
608 AUDIO_SI_WriteReg(ADC_L_GAIN, reg_value);
609
610 reg_value = AUDIO_SI_ReadReg(ADC_R_GAIN);
611 reg_value &= ~(0x7f<<ADC_R_AD_GAIN);
612 reg_value |= (ad_gain_left << ADC_R_AD_GAIN);
613 AUDIO_SI_WriteReg(ADC_R_GAIN, reg_value);
614 }
615
616 /**
617 * @brief Set codec amic boost.
618 * @param amic_bst_left: AMIC left channel boost gain
619 * This parameter can be one of the following values:
620 * @arg 2'b00: 0dB
621 * @arg 2'b01: 20dB
622 * @arg 2'b10: 30dB
623 * @arg 2'b11: 40dB
624 * @param amic_bst_right: AMIC right channel boost gain
625 * This parameter can be one of the following values:
626 * @arg 2'b00: 0dB
627 * @arg 2'b01: 20dB
628 * @arg 2'b10: 30dB
629 * @arg 2'b11: 40dB
630 * @return None
631 */
CODEC_SetAmicBst(u32 amic_bst_left,u32 amic_bst_right)632 void CODEC_SetAmicBst(u32 amic_bst_left, u32 amic_bst_right)
633 {
634 u32 reg_value = 0;
635
636 reg_value = AUDIO_SI_ReadReg(MICBST_CTRL);
637 reg_value &= ~(15<<BIT_MICBST_GSELL);
638 reg_value |= ((amic_bst_left&0x03)|((amic_bst_right&0x03)<<2));
639
640 AUDIO_SI_WriteReg(MICBST_CTRL, reg_value);
641 }
642
643 /**
644 * @brief Set codec dmic boost.
645 * @param dmic_bst_left: DMIC left channel boost gain
646 * This parameter can be one of the following values:
647 * @arg 2'b00: 0dB
648 * @arg 2'b01: 12dB
649 * @arg 2'b10: 24dB
650 * @arg 2'b11: 36dB
651 * @param dmic_bst_right: DMIC right channel boost gain
652 * This parameter can be one of the following values:
653 * @arg 2'b00: 0dB
654 * @arg 2'b01: 12dB
655 * @arg 2'b10: 24dB
656 * @arg 2'b11: 36dB
657 * @return None
658 */
CODEC_SetDmicBst(u32 dmic_bst_left,u32 dmic_bst_right)659 void CODEC_SetDmicBst(u32 dmic_bst_left, u32 dmic_bst_right)
660 {
661 u32 reg_value = 0;
662
663 reg_value = AUDIO_SI_ReadReg(ADC_L_CTRL);
664 reg_value &= ~(3<<BIT_ADC_L_DMIC_BOOST_GAIN);
665 reg_value |= (dmic_bst_left&0x03)<<BIT_ADC_L_DMIC_BOOST_GAIN;
666
667 AUDIO_SI_WriteReg(ADC_L_CTRL, reg_value);
668
669 reg_value = AUDIO_SI_ReadReg(ADC_R_ADJ_D);
670 reg_value &= ~(3<<BIT_ADC_R_DMIC_BOOST_GAIN);
671
672 reg_value |= (dmic_bst_right&0x03)<<BIT_ADC_R_DMIC_BOOST_GAIN;
673 AUDIO_SI_WriteReg(ADC_R_ADJ_D, reg_value);
674 }
675
676 /**
677 * @brief Set MIC_BIAS output voltage.
678 * @param mic_bias: micphone bias voltage setting
679 * This parameter can be one of the following values:
680 * @arg 2'b00: 0.90*AVCC
681 * @arg 2'b01: 0.86*AVCC
682 * @arg 2'b10: 0.75*AVCC
683 * @arg 2'b11: reserved
684 * @note AVCC is 2.8V@3.3V operation mode or 1.7V@1.8V operation mode
685 * @return None
686 */
CODEC_SetMicBias(u8 mic_bias)687 void CODEC_SetMicBias(u8 mic_bias)
688 {
689 u32 reg_value = 0;
690 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL);
691 reg_value &= ~(3<<BIT_MICBIAS_VSET);
692 reg_value |= ((mic_bias&0x03) << BIT_MICBIAS_VSET);
693 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
694 }
695
696 /**
697 * @brief mute or unmute per ad channel.
698 * @param mute_lch: mute option for left ad channel
699 * This parameter can be one of the following values:
700 * @arg MUTE_DISABLE: unmute
701 * @arg MUTE_ENABLE: mute
702 * @arg MUTE_NO_ACT: no modification
703 * @param mute_rch: mute option for right ad channel
704 * This parameter can be one of the following values:
705 * @arg MUTE_DISABLE: unmute
706 * @arg MUTE_ENABLE: mute
707 * @arg MUTE_NO_ACT: no modification
708 * @return None
709 */
CODEC_MuteRecord(u32 mute_lch,u32 mute_rch)710 void CODEC_MuteRecord(u32 mute_lch, u32 mute_rch)
711 {
712 u32 reg_value = 0;
713
714 if (mute_lch == MUTE_ENABLE){
715 reg_value = AUDIO_SI_ReadReg(ADC_L_CTRL); //left ad mute
716 reg_value |= (1<<BIT_ADC_L_AD_MUTE);
717 AUDIO_SI_WriteReg(ADC_L_CTRL, reg_value);
718 }
719 else if (mute_lch == MUTE_DISABLE){
720 reg_value = AUDIO_SI_ReadReg(ADC_L_CTRL); //left ad unmute
721 reg_value &= (0xffff & (~(1<<BIT_ADC_L_AD_MUTE)));
722 AUDIO_SI_WriteReg(ADC_L_CTRL, reg_value);
723 }
724
725 if (mute_rch == MUTE_ENABLE){
726 reg_value = AUDIO_SI_ReadReg(ADC_R_ADJ_D); //right ad mute
727 reg_value |= (1<<BIT_ADC_R_AD_MUTE);
728 AUDIO_SI_WriteReg(ADC_R_ADJ_D, reg_value);
729 }
730 else if (mute_rch == MUTE_DISABLE){
731 reg_value = AUDIO_SI_ReadReg(ADC_R_ADJ_D); //right ad unmute
732 reg_value &= (0xffff & (~(1<<BIT_ADC_R_AD_MUTE)));
733 AUDIO_SI_WriteReg(ADC_R_ADJ_D, reg_value);
734 }
735 return;
736 }
737
738 /**
739 * @brief mute or unmute per da channel.
740 * @param mute_lch: mute option for left da channel
741 * This parameter can be one of the following values:
742 * @arg MUTE_DISABLE: unmute
743 * @arg MUTE_ENABLE: mute
744 * @arg MUTE_NO_ACT: no modification
745 * @param mute_rch: mute option for right da channel
746 * This parameter can be one of the following values:
747 * @arg MUTE_DISABLE: unmute
748 * @arg MUTE_ENABLE: mute
749 * @arg MUTE_NO_ACT: no modification
750 * @return None
751 */
CODEC_MutePlay(u32 mute_lch,u32 mute_rch)752 void CODEC_MutePlay(u32 mute_lch, u32 mute_rch)
753 {
754 u32 reg_value = 0;
755
756 if (mute_lch == MUTE_ENABLE){
757 reg_value = AUDIO_SI_ReadReg(DAC_L_MUTE_CTRL); //left da mut
758 reg_value |= (1<<BIT_DAC_L_DA_MUTE);
759 AUDIO_SI_WriteReg(DAC_L_MUTE_CTRL, reg_value);
760 }
761 else if (mute_lch == MUTE_DISABLE){
762 reg_value = AUDIO_SI_ReadReg(DAC_L_MUTE_CTRL); //left da unmute
763 reg_value &= (0xffff & (~(1<<BIT_DAC_L_DA_MUTE)));
764 AUDIO_SI_WriteReg(DAC_L_MUTE_CTRL, reg_value);
765 }
766
767 if (mute_rch == MUTE_ENABLE){
768 reg_value = AUDIO_SI_ReadReg(DAC_R_MUTE_CTRL); //right da mute
769 reg_value |= (1<<BIT_DAC_R_DA_MUTE);
770 AUDIO_SI_WriteReg(DAC_R_MUTE_CTRL, reg_value);
771 }
772 else if (mute_rch == MUTE_DISABLE){
773 reg_value = AUDIO_SI_ReadReg(DAC_R_MUTE_CTRL); //right da unmute
774 reg_value &= (0xffff & (~(1<<BIT_DAC_R_DA_MUTE)));
775 AUDIO_SI_WriteReg(DAC_R_MUTE_CTRL, reg_value);
776 }
777 return;
778 }
779
780 /**
781 * @brief De-initialize codec peripheral.
782 * @param application: application mode
783 * This parameter can be one of the following values:
784 * @arg APP_AMIC_IN: analog microphone in
785 * @arg APP_DMIC_IN: digital microphone in
786 * @arg APP_LINE_IN: line in
787 * @arg APP_LINE_OUT: line out
788 * @return None
789 */
CODEC_DeInit(u32 application)790 void CODEC_DeInit(u32 application)
791 {
792 u32 reg_value = 0;
793
794 if (((application&APP_AMIC_IN) == APP_AMIC_IN) || ((application&APP_LINE_IN) == APP_LINE_IN)){
795 #if 0
796 reg_value = AUDIO_SI_ReadReg(ADC_DMIC_L_FILTER_CTRL); //left ad filter off
797 reg_value &= ~0x4000;
798 AUDIO_SI_WriteReg(ADC_DMIC_L_FILTER_CTRL, reg_value);
799
800 reg_value = AUDIO_SI_ReadReg(ADC_DMIC_R_FILTER_CTRL); //right ad filter off
801 reg_value &= ~0x4000;
802 AUDIO_SI_WriteReg(ADC_DMIC_R_FILTER_CTRL, reg_value);
803 #endif
804 reg_value = AUDIO_SI_ReadReg(GEN_CTRL); //adc off
805 reg_value &= ~(1<<BIT_DTSDM_POW_L | 1<<BIT_DTSDM_POW_R);
806 AUDIO_SI_WriteReg(GEN_CTRL, reg_value);
807
808 reg_value = AUDIO_SI_ReadReg(MICBST_CTRL); //PGA off and path mute
809 reg_value &= ~(3<<BIT_MICBST_POW);
810 reg_value |= (3<<BIT_MICBST_MUTE_L | 3<<BIT_MICBST_MUTE_R);
811 AUDIO_SI_WriteReg(MICBST_CTRL, reg_value);
812
813 if ((application&APP_AMIC_IN) == APP_AMIC_IN){
814 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL); //mic_bias off
815 reg_value &= ~(1<<BIT_MICBIAS_POW);
816 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
817 }
818 }
819
820 if ((application&APP_DMIC_IN) == APP_DMIC_IN){
821 reg_value = AUDIO_SI_ReadReg(DAC_ADC_MIC_CLK_CTRL);//dmic clock off
822 reg_value &= ~(1<<BIT_DMIC_L_EN | 1<<BIT_DMIC_R_EN | 1<<BIT_DMIC_CLK_EN);
823 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL, reg_value);
824 }
825
826 if ((application&APP_LINE_OUT) == APP_LINE_OUT){
827 reg_value = AUDIO_SI_ReadReg(HPO_CTRL); //amplifier off
828 reg_value &= ~(1<<BIT_HPO_ENAL | 1<<BIT_HPO_ENAR);
829 AUDIO_SI_WriteReg(HPO_CTRL, reg_value);
830
831 reg_value = AUDIO_SI_ReadReg(HPO_MIC_CTRL); //path mute and right channel off
832 reg_value &= ~(1<<BIT_HPO_R_POW);
833 reg_value |= (3<< BIT_HPO_ML | 3<<BIT_HPO_MR);
834 AUDIO_SI_WriteReg(HPO_MIC_CTRL, reg_value);
835
836 reg_value = AUDIO_SI_ReadReg(HPO_CTRL); //left channel off and amplifier off
837 reg_value &= ~(1<<BIT_HPO_L_POW);
838 AUDIO_SI_WriteReg(HPO_CTRL, reg_value);
839
840 reg_value = AUDIO_SI_ReadReg(GEN_CTRL); //dac off
841 reg_value &= ~(1<<BIT_DAC_L_POW | 1<<BIT_DAC_R_POW);
842 AUDIO_SI_WriteReg(GEN_CTRL, reg_value);
843
844 reg_value = AUDIO_SI_ReadReg(DAC_ADC_MIC_CLK_CTRL); //dac modulation/filter/fifo reset
845 reg_value &= ~(1<<BIT_DA_L_EN | 1<<BIT_DA_R_EN | 1<<BIT_MOD_L_EN | 1<<BIT_MOD_R_EN | 1<<BIT_DA_ANA_CLK_EN | 1<<BIT_DA_FIFO_EN);
846 AUDIO_SI_WriteReg(DAC_ADC_MIC_CLK_CTRL, reg_value);
847 }
848 }
849
850 /**
851 * @brief Config codec DA path EQ parameters.
852 * @param sample_rate: codec DAC sample rate.
853 * This parameter can be one of the following values:
854 * @arg SR_8K: sample rate is 8kHz
855 * @arg SR_16K: sample rate is 16kHz
856 * @arg SR_48K: sample rate is 48kHz
857 * @arg SR_44P1K: sample rate is 44.1kHz
858 * @return None
859 */
CODEC_DacEqConfig(u32 sample_rate)860 void CODEC_DacEqConfig(u32 sample_rate)
861 {
862 u32 cnt;
863 u32 eq_en_num;
864 u32 *eq_param;
865
866 switch (sample_rate){
867 case SR_44P1K:
868 eq_en_num = eq_44p1k_en_num;
869 eq_param = (u32 *)eq_param_44p1k;
870 break;
871 case SR_48K:
872 eq_en_num = eq_48k_en_num;
873 eq_param = (u32 *)eq_param_48k;
874 break;
875 case SR_8K:
876 eq_en_num = eq_8k_en_num;
877 eq_param = (u32 *)eq_param_8k;
878 break;
879 case SR_16K:
880 eq_en_num = eq_16k_en_num;
881 eq_param = (u32 *)eq_param_16k;
882 break;
883 default:
884 eq_en_num = 0;
885 break;
886 }
887
888 if (!eq_en_num){
889 return;
890 }
891 for(cnt=0; cnt<eq_en_num*5; cnt++){
892 AUDIO_SI_WriteReg(DAC_L_BIQUAD_H0_1L + cnt*2, (u16)(eq_param[cnt]));
893 AUDIO_SI_WriteReg(DAC_L_BIQUAD_H0_1H + cnt*2, (u16)((eq_param[cnt])>>16));
894 }
895 for(cnt=0; cnt<eq_en_num*5; cnt++){
896 AUDIO_SI_WriteReg(DAC_R_BIQUAD_H0_1L + cnt*2, (u16)(eq_param[cnt]));
897 AUDIO_SI_WriteReg(DAC_R_BIQUAD_H0_1H + cnt*2, (u16)((eq_param[cnt])>>16));
898 }
899
900 AUDIO_SI_WriteReg(DAC_L_BQ_EQ_CTRL, 0x0);
901 AUDIO_SI_WriteReg(DAC_L_BQ_EQ_CTRL, 0x1);
902 AUDIO_SI_WriteReg(DAC_R_BQ_EQ_CONTROL, 0x0);
903 AUDIO_SI_WriteReg(DAC_R_BQ_EQ_CONTROL, 0x1);
904 }
905
906 /**
907 * @brief Enable ALC function and set limiter threshold value
908 * @param limiter_val: ALC main-limiter threshold level (at amplitude domain) control
909 * This parameter can be one of the following values:
910 * @arg 32'h00: 0dB
911 * @arg 32'h01: -0.375dB
912 * @arg 32'h02: -0.750dB
913 * @arg ...
914 * @arg 32'h3F: -23.625dB
915 * @return None
916 */
CODEC_SetALC(u32 limiter_val)917 void CODEC_SetALC(u32 limiter_val)
918 {
919 u32 reg_value = AUDIO_SI_ReadReg(ALC_DRC_CTRL);
920 reg_value |= (1 | 1 << 6);
921 AUDIO_SI_WriteReg(ALC_DRC_CTRL, reg_value);
922
923 reg_value = AUDIO_SI_ReadReg(ALC_RATE_CTRL);
924 reg_value |= (limiter_val << 10);
925 AUDIO_SI_WriteReg(ALC_RATE_CTRL, reg_value);
926 }
927
928 /**
929 * @brief De-initialize ALC function.
930 * @param None
931 * @return None
932 */
CODEC_ALC_deinit()933 void CODEC_ALC_deinit()
934 {
935 u32 reg_value = AUDIO_SI_ReadReg(ALC_DRC_CTRL);
936 reg_value &= (~(1 | 1 << 6));
937 AUDIO_SI_WriteReg(ALC_DRC_CTRL, reg_value);
938 }
939
940 /******************* (C) COPYRIGHT 2018 Realtek Semiconductor *****END OF FILE****/
941