1 /** 2 ****************************************************************************** 3 * @file rtl8721d_audio.h 4 * @author 5 * @version V1.0.0 6 * @date 2017-12-13 7 * @brief This file contains all the functions prototypes for the audio codec firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8721D_AUDIO_H_ 20 #define _RTL8721D_AUDIO_H_ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @defgroup audio 27 * @brief audio driver modules 28 * @{ 29 */ 30 31 /** @addtogroup audio 32 * @verbatim 33 ***************************************************************************************** 34 * Introduction 35 ***************************************************************************************** 36 * audio sport: 37 * - Base Address: AUDIO_SPORT_DEV 38 * - Source clk: 40MHz or 45.1584MHz or 98.304MHz(default) 39 * - Sample rate: 8/16/32/44.1/48/88.2/96 /11.025/12/22.05 KHz 40 * - Sample bit: 16 bit, 24 bit, 8bit 41 * - Channel number: mono or stereo 42 * - Data format: I2S, Left justified, PCM mode A, PCM mode B, PCM mode A-N, PCM mode B-N 43 * - Use GDMA to move data 44 * 45 ***************************************************************************************** 46 * How to use audio sport 47 ***************************************************************************************** 48 * To use audio codec sport, the following steps are mandatory: 49 * 50 * 1. Open audio codec clock and function using 51 * PLLx_Set(0, ENABLE); (x is 0 or 1) 52 * RCC_PeriphClockCmd(APBPeriph_AUDIOC, APBPeriph_AUDIOC_CLOCK, ENABLE); 53 * RCC_PeriphClockCmd(APBPeriph_SPORT, APBPeriph_SPORT_CLOCK, ENABLE); 54 * 55 * 2. AUDIO SPORT pin setting: 56 * PAD_CMD(PinName, DISABLE). 57 * 58 * 3. Fill the AUDIO_SP_InitStruct with the desired parameters. 59 * 60 * 4. configure AUDIO SPORT with the corresponding configuration. 61 * AUDIO_SP_Init(AUDIO_SP_DEV, &SP_InitStruct) 62 * 63 * 5. According to audio codec transfer direction, start Tx or Rx or both path 64 * start Tx path: 65 * AUDIO_SP_TdmaCmd(AUDIO_SPORT_DEV, ENABLE); 66 * AUDIO_SP_TxStart(AUDIO_SPORT_DEV, ENABLE); 67 * start Rx path: 68 * AUDIO_SP_RdmaCmd(AUDIO_SPORT_DEV, ENABLE); 69 * AUDIO_SP_RxStart(AUDIO_SPORT_DEV, ENABLE); 70 * 71 * 6. Use AUDIO_SP_TXGDMA_Init or AUDIO_SP_RXGDMA_Init or both function to activate the GDMA according to transfer direction. 72 * 73 * @note All other functions can be used separately to modify, if needed, 74 * a specific feature of the AUDIO SPORT. 75 ***************************************************************************************** 76 * @endverbatim 77 */ 78 79 /* Exported types ------------------------------------------------------------*/ 80 81 /** @defgroup AUDIO_Exported_Types AUDIO Exported Types 82 * @{ 83 */ 84 85 /** 86 * @brief AUDIO SPORT Init structure definition 87 */ 88 typedef struct { 89 u32 SP_WordLen; /*!< Specifies the AUDIO SPORT word length 90 This parameter can be a value of @ref SP_word_length */ 91 92 u32 SP_DataFormat; /*!< Specifies the AUDIO SPORT data format 93 This parameter can be a value of @ref SP_data_format */ 94 95 u32 SP_MonoStereo; /*!< Specifies the AUDIO SPORT channel number 96 This parameter can be a value of @ref SP_channel_number */ 97 98 u32 SP_SelRxCh; /*!< Specifies the AUDIO SPORT selection of RX channel for ADC path 99 This parameter can be a value of @ref SP_SEL_RX_channel */ 100 } SP_InitTypeDef; 101 /** 102 * @} 103 */ 104 105 /* Exported constants --------------------------------------------------------*/ 106 107 /** @defgroup AUDIO_Exported_Constants AUDIO Exported Constants 108 * @{ 109 */ 110 111 /** @defgroup SP_word_length AUDIO SPORT Word Length 112 * @{ 113 */ 114 #define SP_WL_16 ((u32)0x00000000) 115 #define SP_WL_24 ((u32)0x00000002) 116 #define SP_WL_8 ((u32)0x00000003) 117 118 #define IS_SP_WORD_LEN(LEN) (((LEN) == SP_WL_16) || \ 119 ((LEN) == SP_WL_24) || \ 120 ((LEN) == SP_WL_8)) 121 122 /** 123 * @} 124 */ 125 126 /** @defgroup SP_data_format AUDIO SPORT Interface Format 127 * @{ 128 */ 129 #define SP_DF_I2S ((u32)0x00000000) 130 #define SP_DF_LEFT ((u32)0x00000001) 131 #define SP_DF_PCM_A ((u32)0x00000002) 132 #define SP_DF_PCM_B ((u32)0x00000003) 133 #define SP_DF_PCM_AN ((u32)0x00000006) 134 #define SP_DF_PCM_BN ((u32)0x00000007) 135 136 #define IS_SP_DATA_FMT(FORMAT) (((FORMAT) == SP_DF_I2S) || \ 137 ((FORMAT) == SP_DF_LEFT) || \ 138 ((FORMAT) == SP_DF_PCM_A) || \ 139 ((FORMAT) == SP_DF_PCM_B) || \ 140 ((FORMAT) == SP_DF_PCM_AN) || \ 141 ((FORMAT) == SP_DF_PCM_BN)) 142 143 /** 144 * @} 145 */ 146 147 /** @defgroup SP_channel_number AUDIO SPORT Channel Number 148 * @{ 149 */ 150 #define SP_CH_STEREO ((u32)0x00000000) 151 #define SP_CH_MONO ((u32)0x00000001) 152 153 #define IS_SP_CHN_NUM(NUM) (((NUM) == SP_CH_STEREO) || \ 154 ((NUM) == SP_CH_MONO)) 155 156 /** 157 * @} 158 */ 159 160 /** @defgroup SP_SEL_RX_channel AUDIO SPORT Selection of RX Channel 161 * @{ 162 */ 163 #define SP_RX_CH_LR ((u32)0x00000000) 164 #define SP_RX_CH_RL ((u32)0x00000001) 165 #define SP_RX_CH_LL ((u32)0x00000002) 166 #define SP_RX_CH_RR ((u32)0x00000003) 167 168 #define IS_SP_SEL_RX_CH(CH) (((CH) == SP_RX_CH_LR) || \ 169 ((CH) == SP_RX_CH_RL) || \ 170 ((CH) == SP_RX_CH_LL) || \ 171 ((CH) == SP_RX_CH_RR)) 172 173 /** 174 * @} 175 */ 176 177 /** 178 * @} 179 */ 180 181 /* Exported functions --------------------------------------------------------*/ 182 /** @defgroup AUDIO_Exported_Functions AUDIO Exported Functions 183 * @{ 184 */ 185 186 /** @defgroup AUDIO_SPORT_functions 187 * @{ 188 */ 189 _LONG_CALL_ void AUDIO_SP_StructInit(SP_InitTypeDef* SP_InitStruct); 190 _LONG_CALL_ void AUDIO_SP_Init(AUDIO_SPORT_TypeDef* SPORTx, SP_InitTypeDef* SP_InitStruct); 191 _LONG_CALL_ void AUDIO_SP_TxStart(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState); 192 _LONG_CALL_ void AUDIO_SP_RxStart(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState); 193 _LONG_CALL_ void AUDIO_SP_TdmaCmd(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState); 194 _LONG_CALL_ void AUDIO_SP_RdmaCmd(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState); 195 _LONG_CALL_ void AUDIO_SP_SetWordLen(AUDIO_SPORT_TypeDef* SPORTx, u32 SP_WordLen); 196 _LONG_CALL_ u32 AUDIO_SP_GetWordLen(AUDIO_SPORT_TypeDef* SPORTx); 197 _LONG_CALL_ void AUDIO_SP_SetMonoStereo(AUDIO_SPORT_TypeDef* SPORTx, u32 SP_MonoStereo); 198 _LONG_CALL_ BOOL AUDIO_SP_TXGDMA_Init(u32 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length); 199 _LONG_CALL_ BOOL AUDIO_SP_RXGDMA_Init(u32 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length); 200 /** 201 * @} 202 */ 203 /** 204 * @} 205 */ 206 207 /* Registers Definitions --------------------------------------------------------*/ 208 /**************************************************************************//** 209 * @defgroup AUDIO_Register_Definitions AUDIO Register Definitions 210 * @{ 211 *****************************************************************************/ 212 213 /**************************************************************************//** 214 * @defgroup AUDIO_SI_Register_Definitions AUDIO SI Register Definitions 215 * @{ 216 *****************************************************************************/ 217 218 /**************************************************************************//** 219 * @defgroup SI_CTRLR 220 * @{ 221 *****************************************************************************/ 222 #define BIT_CTRLR_SI_WR_START ((u32)0x00000001 << 0) 223 #define BIT_CTRLR_SI_RD_START ((u32)0x00000001 << 4) 224 #define BIT_CTRLR_SI_DISABLE ((u32)0x00000001 << 7) 225 #define BIT_CTRLR_SI_ADDR ((u32)0x000000FF << 8) 226 #define BIT_CTRLR_SI_DATA ((u32)0x0000FFFF << 16) 227 /** @} */ 228 229 /**************************************************************************//** 230 * @defgroup SI_CLK_EN 231 * @{ 232 *****************************************************************************/ 233 #define BIT_SI_CLK_EN ((u32)0x00000001 << 0) 234 /** @} */ 235 /** @} */ 236 237 /**************************************************************************//** 238 * @defgroup AUDIO_SPORT_Register_Definitions AUDIO SPORT Register Definitions 239 * @{ 240 *****************************************************************************/ 241 242 /**************************************************************************//** 243 * @defgroup SP_CTRLR0 244 * @{ 245 *****************************************************************************/ 246 #define SP_CTRLR0_RST ((u32)0x00000001 << 0) /* Bit[0], reset SPORT1 module*/ 247 #define SP_CTRLR0_TX_INV_I2S_SCLK ((u32)0x00000001 << 1) /* Bit[1], invert sclk to TX path (DAC path)*/ 248 #define SP_CTRLR0_RX_INV_I2S_SCLK ((u32)0x00000001 << 2) /* Bit[2], invert sclk to RX path (ADC path)*/ 249 #define SP_CTRLR0_SLAVE_CLK_SEL ((u32)0x00000001 << 3) /* Bit[3], To be an I2S or PCM slave (CLK path)*/ 250 #define SP_CTRLR0_SLAVE_DATA_SEL ((u32)0x00000001 << 4) /* Bit[4], To be an I2S or PCM slave (data path)*/ 251 #define SP_CTRLR0_WCLK_INV ((u32)0x00000001 << 5) /* Bit[5], invert I2S/PCM word clock*/ 252 #define SP_CTRLR0_LOOPBACK ((u32)0x00000001 << 6) /* Bit[6], self loopback mode*/ 253 #define SP_CTRLR0_DSP_CTL_MODE ((u32)0x00000001 << 7) /* Bit[7], 1: DSP and SPORT1 handshaking is enabled; 0: GDMA and SPORT1 handshaking is enabled*/ 254 #define SP_CTRLR0_DATA_FORMAT_SEL ((u32)0x00000003 << 8) /* Bit[9:8], data format*/ 255 #define SP_CTRLR0_EN_PCM_N_MODE_SEL ((u32)0x00000001 << 10)/* Bit[10], pcm n mode*/ 256 #define SP_CTRLR0_EN_I2S_MONO ((u32)0x00000001 << 11)/* Bit[11], 1: mono; 0: stereo*/ 257 #define SP_CTRLR0_DATA_LEN_SEL ((u32)0x00000003 << 12)/* Bit[13:12], data len*/ 258 #define SP_CTRLR0_INV_I2S_SCLK ((u32)0x00000001 << 14)/* Bit[14], invert I2S/PCM bit clock*/ 259 #define SP_CTRLR0_I2S_SELF_LPBK_EN ((u32)0x00000001 << 15)/* Bit[15], internal loopback mode*/ 260 #define SP_CTRLR0_TX_DISABLE ((u32)0x00000001 << 16)/* Bit[16], disable or enable SPORT TX*/ 261 #define SP_CTRLR0_START_TX ((u32)0x00000001 << 17)/* Bit[17], TX start*/ 262 #define SP_CTRLR0_ADC_COMP ((u32)0x00000003 << 18)/* Bit[19:18], ADC compress*/ 263 #define SP_CTRLR0_SEl_I2S_TX_CH ((u32)0x00000003 << 20)/* Bit[21:20], I2S TX channel select @ DAC path*/ 264 #define SP_CTRLR0_TX_LSB_FIRST ((u32)0x00000001 << 22)/* Bit[22], TX MSB or LSB first select*/ 265 #define SP_CTRLR0_RX_LSB_FIRST ((u32)0x00000001 << 23)/* Bit[23], RX MSB or LSB first select*/ 266 #define SP_CTRLR0_RX_DISABLE ((u32)0x00000001 << 24)/* Bit[24], disable or enable SPORT RX*/ 267 #define SP_CTRLR0_START_RX ((u32)0x00000001 << 25)/* Bit[25], RX start*/ 268 #define SP_CTRLR0_DAC_COMP ((u32)0x00000003 << 26)/* Bit[27:26], DAC compress*/ 269 #define SP_CTRLR0_SEL_I2S_RX_CH ((u32)0x00000003 << 28)/* Bit[29:28], I2S RX channel select @ ADC path*/ 270 #define SP_CTRLR0_MCLK_SEL ((u32)0x00000001 << 30)/* Bit[30], MCLK output select*/ 271 #define SP_CTRLR0_LONG_FRAME_SYNC ((u32)0x00000001 << 31)/* Bit[31], short frame sync or long frame sync select*/ 272 /** @} */ 273 274 /**************************************************************************//** 275 * @defgroup SP_CTRLR1 276 * @{ 277 *****************************************************************************/ 278 #define SP_CTRLR1_FRAME_SYNC_OFFSET ((u32)0x000000FF) /* Bit[7:0], To control the length of "long_frame_sync" signal when it is ON.*/ 279 #define SP_CTRLR1_DEBUG_BUS_SEL ((u32)0x00000007 << 8) /* Bit[10:8], debug_bus*/ 280 #define SP_CTRLR1_CLEAR_TX_ERR_CNT ((u32)0x00000001 << 12)/* Bit[12], clear TX error counter*/ 281 #define SP_CTRLR1_CLEAR_RX_ERR_CNT ((u32)0x00000001 << 13)/* Bit[13], clear RX error counter*/ 282 #define SP_CTRLR1_MODE_40MHZ ((u32)0x00000001 << 16)/* Bit[16], clock source is 40MHz or not*/ 283 #define SP_CTRLR1_MODE_128FS ((u32)0x00000001 << 17)/* Bit[17], clock source is 128*fs or not*/ 284 #define SP_CTRLR1_TDMA_REQ ((u32)0x00000001 << 18)/* Bit[18], Tx DAM request*/ 285 #define SP_CTRLR1_RDMA_REQ ((u32)0x00000001 << 19)/* Bit[19], Rx DAM request*/ 286 #define SP_CTRLR1_TX_SRC_BYTE_SWAP ((u32)0x00000001 << 20)/* Bit[20], swap H/L bytes read from the source memory*/ 287 #define SP_CTRLR1_TX_SRC_LR_SWAP ((u32)0x00000001 << 21)/* Bit[21], swap L/R audio samples read from the source memory*/ 288 #define SP_CTRLR1_RX_SNK_BYTE_SWAP ((u32)0x00000001 << 22)/* Bit[22], swap H/L bytes written to the sink memory*/ 289 #define SP_CTRLR1_RX_SNK_LR_SWAP ((u32)0x00000001 << 23)/* Bit[23], swap L/R audio samples written to the sink memory*/ 290 #define SP_CTRLR1_INT_ENABLE ((u32)0x000000FF << 24)/* Bit[31:24], for the interrupt of "sp_ready_to_tx"/"sp_ready_to_rx" */ 291 /** @} */ 292 293 /**************************************************************************//** 294 * @defgroup SP_DSP_INT_CR 295 * @{ 296 *****************************************************************************/ 297 #define SP_TX_DSP_CLEAR_INT ((u32)0x00000001<<0) /* Bit[0], clear TX interrupt (DSP mode) */ 298 #define SP_RX_DSP_CLEAR_INT ((u32)0x00000001<<1) /* Bit[1], clear RX interrupt (DSP mode)*/ 299 #define SP_TX_FIFO_DEPTH_HALF_SEL ((u32)0x00000001<<4) /* Bit[4], 1'b1 TX FIFO depth will reduce to half. It can reduce the data path latency*/ 300 #define SP_RX_FIFO_DEPTH_HALF_SEL ((u32)0x00000001<<5) /* Bit[5], 1'b1 RX FIFO depth will reduce to half. It can reduce the data path latency*/ 301 #define SP_TX_DMA_SINGLE_NO_REQ ((u32)0x00000001<<18) /* Bit[18], 1'b1 TX dma single no request*/ 302 #define SP_RX_DMA_SINGLE_NO_REQ ((u32)0x00000001<<19) /* Bit[19], 1'b1 RX dma single no request*/ 303 /** @} */ 304 305 /**************************************************************************//** 306 * @defgroup SP_FIFO_SR 307 * @{ 308 *****************************************************************************/ 309 #define SP_TX0_WCNT_BUS ((u32)0x000000FF<<0) /* Bit[7:0],TX0 FIFO write counter status (SPK path)*/ 310 #define SP_TX1_WCNT_BUS ((u32)0x000000FF<<8) /* Bit[15:8],TX1 FIFO write counter status (SPK path)*/ 311 #define SP_RX0_RCNT_BUS ((u32)0x000000FF<<16) /* Bit[23:16],RX0 FIFO read counter status (MIC path)*/ 312 #define SP_RX1_RCNT_BUS ((u32)0x000000FF<<24) /* Bit[31:24],RX1 FIFO read counter status (MIC path)*/ 313 /** @} */ 314 315 /**************************************************************************//** 316 * @defgroup SP_ERROR_CNT_SR 317 * @{ 318 *****************************************************************************/ 319 #define SP_TX_ERR_CNT ((u32)0x000000FF<<0) /* Bit[7:0],TX error counter (SPK path)*/ 320 #define SP_RX_ERR_CNT ((u32)0x000000FF<<8) /* Bit[15:8],RX error counter (MIC path)*/ 321 /** @} */ 322 323 /**************************************************************************//** 324 * @defgroup SP_CLK_DIV 325 * @{ 326 *****************************************************************************/ 327 #define SP_CLK_MI ((u32)0x0000FFFF<<0) /* Bit[15:0],BCLK clock divider */ 328 #define SP_CLK_NI ((u32)0x00007FFF<<16) /* Bit[30:16],BCLK clock divider */ 329 #define SP_CLK_MI_NI_UPDATE ((u32)0x00000001<<31) /* Bit[31],update "mi" and "ni" to get the new clock rate */ 330 /** @} */ 331 /** @} */ 332 /** @} */ 333 334 /** 335 * @} 336 */ 337 338 /** 339 * @} 340 */ 341 /* Other Definitions --------------------------------------------------------*/ 342 typedef struct 343 { 344 AUDIO_SPORT_TypeDef* SPORTx; 345 u32 Tx_HandshakeInterface; 346 u32 Rx_HandshakeInterface; 347 } AUDIO_DevTable; 348 349 extern const AUDIO_DevTable AUDIO_DEV_TABLE[1]; 350 #define AUDIO_BLOCK_SIZE 2048 351 #endif /* _RTL8721D_I2S_H_ */ 352 353 /******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/ 354