1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 if !TFABOOT 5 select FSL_LAYERSCAPE 6 select FSL_LSCH2 7 select GICV2 8 select SKIP_LOWLEVEL_INIT 9 select SYS_FSL_SRDS_1 10 select SYS_HAS_SERDES 11 select SYS_FSL_DDR_BE 12 select SYS_FSL_MMDC 13 select SYS_FSL_ERRATUM_A010315 14 select SYS_FSL_ERRATUM_A009798 15 select SYS_FSL_ERRATUM_A008997 16 select SYS_FSL_ERRATUM_A009007 17 select SYS_FSL_ERRATUM_A009008 18 select ARCH_EARLY_INIT_R 19 select BOARD_EARLY_INIT_F 20 select SYS_I2C_MXC 21 select SYS_I2C_MXC_I2C1 if !DM_I2C 22 select SYS_I2C_MXC_I2C2 if !DM_I2C 23 imply PANIC_HANG 24 25config ARCH_LS1028A 26 bool 27 select ARMV8_SET_SMPEN 28 select FSL_LAYERSCAPE 29 select FSL_LSCH3 30 select GICV3 31 select NXP_LSCH3_2 32 select SYS_FSL_HAS_CCI400 33 select SYS_FSL_SRDS_1 34 select SYS_HAS_SERDES 35 select SYS_FSL_DDR 36 select SYS_FSL_DDR_LE 37 select SYS_FSL_DDR_VER_50 38 select SYS_FSL_HAS_DDR3 39 select SYS_FSL_HAS_DDR4 40 select SYS_FSL_HAS_SEC 41 select SYS_FSL_SEC_COMPAT_5 42 select SYS_FSL_SEC_LE 43 select FSL_TZASC_1 44 select ARCH_EARLY_INIT_R 45 select BOARD_EARLY_INIT_F 46 select SYS_I2C_MXC 47 select SYS_FSL_ERRATUM_A008997 48 select SYS_FSL_ERRATUM_A009007 49 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 50 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 51 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 52 select SYS_FSL_ERRATUM_A050382 53 select SYS_FSL_ERRATUM_A011334 54 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 55 select RESV_RAM if GIC_V3_ITS 56 imply PANIC_HANG 57 58config ARCH_LS1043A 59 bool 60 select ARMV8_SET_SMPEN 61 select ARM_ERRATA_855873 if !TFABOOT 62 select FSL_LAYERSCAPE 63 select FSL_LSCH2 64 select GICV2 65 select HAS_FSL_XHCI_USB if USB_HOST 66 select SKIP_LOWLEVEL_INIT 67 select SYS_FSL_SRDS_1 68 select SYS_HAS_SERDES 69 select SYS_FSL_DDR 70 select SYS_FSL_DDR_BE 71 select SYS_FSL_DDR_VER_50 72 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 73 select SYS_FSL_ERRATUM_A008997 74 select SYS_FSL_ERRATUM_A009007 75 select SYS_FSL_ERRATUM_A009008 76 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 77 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 78 select SYS_FSL_ERRATUM_A009798 79 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 80 select SYS_FSL_ERRATUM_A010315 81 select SYS_FSL_ERRATUM_A010539 82 select SYS_FSL_HAS_DDR3 83 select SYS_FSL_HAS_DDR4 84 select ARCH_EARLY_INIT_R 85 select BOARD_EARLY_INIT_F 86 select SYS_I2C_MXC 87 select SYS_I2C_MXC_I2C1 if !DM_I2C 88 select SYS_I2C_MXC_I2C2 if !DM_I2C 89 select SYS_I2C_MXC_I2C3 if !DM_I2C 90 select SYS_I2C_MXC_I2C4 if !DM_I2C 91 imply CMD_PCI 92 imply ID_EEPROM 93 94config ARCH_LS1046A 95 bool 96 select ARMV8_SET_SMPEN 97 select FSL_LAYERSCAPE 98 select FSL_LSCH2 99 select GICV2 100 select HAS_FSL_XHCI_USB if USB_HOST 101 select SKIP_LOWLEVEL_INIT 102 select SYS_FSL_SRDS_1 103 select SYS_HAS_SERDES 104 select SYS_FSL_DDR 105 select SYS_FSL_DDR_BE 106 select SYS_FSL_DDR_VER_50 107 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 108 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 109 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 110 select SYS_FSL_ERRATUM_A008997 111 select SYS_FSL_ERRATUM_A009007 112 select SYS_FSL_ERRATUM_A009008 113 select SYS_FSL_ERRATUM_A009798 114 select SYS_FSL_ERRATUM_A009801 115 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 116 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 117 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 118 select SYS_FSL_ERRATUM_A010539 119 select SYS_FSL_HAS_DDR4 120 select SYS_FSL_SRDS_2 121 select ARCH_EARLY_INIT_R 122 select BOARD_EARLY_INIT_F 123 select SYS_I2C_MXC 124 select SYS_I2C_MXC_I2C1 if !DM_I2C 125 select SYS_I2C_MXC_I2C2 if !DM_I2C 126 select SYS_I2C_MXC_I2C3 if !DM_I2C 127 select SYS_I2C_MXC_I2C4 if !DM_I2C 128 imply ID_EEPROM 129 imply SCSI 130 imply SCSI_AHCI 131 imply SPL_SYS_I2C_LEGACY 132 133config ARCH_LS1088A 134 bool 135 select ARMV8_SET_SMPEN 136 select ARM_ERRATA_855873 if !TFABOOT 137 select FSL_LAYERSCAPE 138 select FSL_LSCH3 139 select GICV3 140 select SKIP_LOWLEVEL_INIT 141 select SYS_FSL_SRDS_1 142 select SYS_HAS_SERDES 143 select SYS_FSL_DDR 144 select SYS_FSL_DDR_LE 145 select SYS_FSL_DDR_VER_50 146 select SYS_FSL_EC1 147 select SYS_FSL_EC2 148 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 149 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 150 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 151 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 152 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 153 select SYS_FSL_ERRATUM_A009007 154 select SYS_FSL_HAS_CCI400 155 select SYS_FSL_HAS_DDR4 156 select SYS_FSL_HAS_RGMII 157 select SYS_FSL_HAS_SEC 158 select SYS_FSL_SEC_COMPAT_5 159 select SYS_FSL_SEC_LE 160 select SYS_FSL_SRDS_1 161 select SYS_FSL_SRDS_2 162 select FSL_TZASC_1 163 select FSL_TZASC_400 164 select FSL_TZPC_BP147 165 select ARCH_EARLY_INIT_R 166 select BOARD_EARLY_INIT_F 167 select SYS_I2C_MXC 168 select SYS_I2C_MXC_I2C1 if !TFABOOT 169 select SYS_I2C_MXC_I2C2 if !TFABOOT 170 select SYS_I2C_MXC_I2C3 if !TFABOOT 171 select SYS_I2C_MXC_I2C4 if !TFABOOT 172 select RESV_RAM if GIC_V3_ITS 173 imply ID_EEPROM 174 imply SCSI 175 imply SPL_SYS_I2C_LEGACY 176 imply PANIC_HANG 177 178config ARCH_LS2080A 179 bool 180 select ARMV8_SET_SMPEN 181 select ARM_ERRATA_826974 182 select ARM_ERRATA_828024 183 select ARM_ERRATA_829520 184 select ARM_ERRATA_833471 185 select FSL_LAYERSCAPE 186 select FSL_LSCH3 187 select GICV3 188 select SKIP_LOWLEVEL_INIT 189 select SYS_FSL_SRDS_1 190 select SYS_HAS_SERDES 191 select SYS_FSL_DDR 192 select SYS_FSL_DDR_LE 193 select SYS_FSL_DDR_VER_50 194 select SYS_FSL_HAS_CCN504 195 select SYS_FSL_HAS_DP_DDR 196 select SYS_FSL_HAS_SEC 197 select SYS_FSL_HAS_DDR4 198 select SYS_FSL_SEC_COMPAT_5 199 select SYS_FSL_SEC_LE 200 select SYS_FSL_SRDS_2 201 select FSL_TZASC_1 202 select FSL_TZASC_2 203 select FSL_TZASC_400 204 select FSL_TZPC_BP147 205 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 206 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 207 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 208 select SYS_FSL_ERRATUM_A008585 209 select SYS_FSL_ERRATUM_A008997 210 select SYS_FSL_ERRATUM_A009007 211 select SYS_FSL_ERRATUM_A009008 212 select SYS_FSL_ERRATUM_A009635 213 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 214 select SYS_FSL_ERRATUM_A009798 215 select SYS_FSL_ERRATUM_A009801 216 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 217 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 218 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 219 select SYS_FSL_ERRATUM_A009203 220 select ARCH_EARLY_INIT_R 221 select BOARD_EARLY_INIT_F 222 select SYS_I2C_MXC 223 select SYS_I2C_MXC_I2C1 if !TFABOOT 224 select SYS_I2C_MXC_I2C2 if !TFABOOT 225 select SYS_I2C_MXC_I2C3 if !TFABOOT 226 select SYS_I2C_MXC_I2C4 if !TFABOOT 227 select RESV_RAM if GIC_V3_ITS 228 imply DISTRO_DEFAULTS 229 imply ID_EEPROM 230 imply PANIC_HANG 231 imply SPL_SYS_I2C_LEGACY 232 233config ARCH_LX2162A 234 bool 235 select ARMV8_SET_SMPEN 236 select FSL_LSCH3 237 select GICV3 238 select NXP_LSCH3_2 239 select SYS_HAS_SERDES 240 select SYS_FSL_SRDS_1 241 select SYS_FSL_SRDS_2 242 select SYS_FSL_DDR 243 select SYS_FSL_DDR_LE 244 select SYS_FSL_DDR_VER_50 245 select SYS_FSL_EC1 246 select SYS_FSL_EC2 247 select SYS_FSL_ERRATUM_A050204 248 select SYS_FSL_ERRATUM_A011334 249 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 250 select SYS_FSL_HAS_RGMII 251 select SYS_FSL_HAS_SEC 252 select SYS_FSL_HAS_CCN508 253 select SYS_FSL_HAS_DDR4 254 select SYS_FSL_SEC_COMPAT_5 255 select SYS_FSL_SEC_LE 256 select ARCH_EARLY_INIT_R 257 select BOARD_EARLY_INIT_F 258 select SYS_I2C_MXC 259 select RESV_RAM if GIC_V3_ITS 260 imply DISTRO_DEFAULTS 261 imply PANIC_HANG 262 imply SCSI 263 imply SCSI_AHCI 264 imply SPL_SYS_I2C_LEGACY 265 266config ARCH_LX2160A 267 bool 268 select ARMV8_SET_SMPEN 269 select FSL_LSCH3 270 select GICV3 271 select HAS_FSL_XHCI_USB if USB_HOST 272 select NXP_LSCH3_2 273 select SYS_HAS_SERDES 274 select SYS_FSL_SRDS_1 275 select SYS_FSL_SRDS_2 276 select SYS_NXP_SRDS_3 277 select SYS_FSL_DDR 278 select SYS_FSL_DDR_LE 279 select SYS_FSL_DDR_VER_50 280 select SYS_FSL_EC1 281 select SYS_FSL_EC2 282 select SYS_FSL_ERRATUM_A050204 283 select SYS_FSL_ERRATUM_A011334 284 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 285 select SYS_FSL_HAS_RGMII 286 select SYS_FSL_HAS_SEC 287 select SYS_FSL_HAS_CCN508 288 select SYS_FSL_HAS_DDR4 289 select SYS_FSL_SEC_COMPAT_5 290 select SYS_FSL_SEC_LE 291 select ARCH_EARLY_INIT_R 292 select BOARD_EARLY_INIT_F 293 select SYS_I2C_MXC 294 select RESV_RAM if GIC_V3_ITS 295 imply DISTRO_DEFAULTS 296 imply ID_EEPROM 297 imply PANIC_HANG 298 imply SCSI 299 imply SCSI_AHCI 300 imply SPL_SYS_I2C_LEGACY 301 302config FSL_LSCH2 303 bool 304 select SKIP_LOWLEVEL_INIT 305 select SYS_FSL_HAS_CCI400 306 select SYS_FSL_HAS_SEC 307 select SYS_FSL_SEC_COMPAT_5 308 select SYS_FSL_SEC_BE 309 310config FSL_LSCH3 311 select ARCH_MISC_INIT 312 bool 313 314config NXP_LSCH3_2 315 bool 316 317menu "Layerscape architecture" 318 depends on FSL_LSCH2 || FSL_LSCH3 319 320config FSL_LAYERSCAPE 321 bool 322 323config HAS_FEATURE_GIC64K_ALIGN 324 bool 325 default y if ARCH_LS1043A 326 327config HAS_FEATURE_ENHANCED_MSI 328 bool 329 default y if ARCH_LS1043A 330 331menu "Layerscape PPA" 332config FSL_LS_PPA 333 bool "FSL Layerscape PPA firmware support" 334 depends on !ARMV8_PSCI 335 select ARMV8_SEC_FIRMWARE_SUPPORT 336 select SEC_FIRMWARE_ARMV8_PSCI 337 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 338 help 339 The FSL Primary Protected Application (PPA) is a software component 340 which is loaded during boot stage, and then remains resident in RAM 341 and runs in the TrustZone after boot. 342 Say y to enable it. 343 344config SPL_FSL_LS_PPA 345 bool "FSL Layerscape PPA firmware support for SPL build" 346 depends on !ARMV8_PSCI 347 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 348 select SEC_FIRMWARE_ARMV8_PSCI 349 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 350 help 351 The FSL Primary Protected Application (PPA) is a software component 352 which is loaded during boot stage, and then remains resident in RAM 353 and runs in the TrustZone after boot. This is to load PPA during SPL 354 stage instead of the RAM version of U-Boot. Once PPA is initialized, 355 the rest of U-Boot (including RAM version) runs at EL2. 356choice 357 prompt "FSL Layerscape PPA firmware loading-media select" 358 depends on FSL_LS_PPA 359 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 360 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 361 default SYS_LS_PPA_FW_IN_XIP 362 363config SYS_LS_PPA_FW_IN_XIP 364 bool "XIP" 365 help 366 Say Y here if the PPA firmware locate at XIP flash, such 367 as NOR or QSPI flash. 368 369config SYS_LS_PPA_FW_IN_MMC 370 bool "eMMC or SD Card" 371 help 372 Say Y here if the PPA firmware locate at eMMC/SD card. 373 374config SYS_LS_PPA_FW_IN_NAND 375 bool "NAND" 376 help 377 Say Y here if the PPA firmware locate at NAND flash. 378 379endchoice 380 381config LS_PPA_ESBC_HDR_SIZE 382 hex "Length of PPA ESBC header" 383 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 384 default 0x2000 385 help 386 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 387 NAND to memory to validate PPA image. 388 389endmenu 390 391config SYS_FSL_ERRATUM_A008997 392 bool "Workaround for USB PHY erratum A008997" 393 394config SYS_FSL_ERRATUM_A009007 395 bool 396 help 397 Workaround for USB PHY erratum A009007 398 399config SYS_FSL_ERRATUM_A009008 400 bool "Workaround for USB PHY erratum A009008" 401 402config SYS_FSL_ERRATUM_A009798 403 bool "Workaround for USB PHY erratum A009798" 404 405config SYS_FSL_ERRATUM_A050204 406 bool "Workaround for USB PHY erratum A050204" 407 help 408 USB3.0 Receiver needs to enable fixed equalization 409 for each of PHY instances in an SOC. This is similar 410 to erratum A-009007, but this one is for LX2160A and LX2162A, 411 and the register value is different. 412 413config SYS_FSL_ERRATUM_A010315 414 bool "Workaround for PCIe erratum A010315" 415 416config SYS_FSL_ERRATUM_A010539 417 bool "Workaround for PIN MUX erratum A010539" 418 419config MAX_CPUS 420 int "Maximum number of CPUs permitted for Layerscape" 421 default 2 if ARCH_LS1028A 422 default 4 if ARCH_LS1043A 423 default 4 if ARCH_LS1046A 424 default 16 if ARCH_LS2080A 425 default 8 if ARCH_LS1088A 426 default 16 if ARCH_LX2160A 427 default 16 if ARCH_LX2162A 428 default 1 429 help 430 Set this number to the maximum number of possible CPUs in the SoC. 431 SoCs may have multiple clusters with each cluster may have multiple 432 ports. If some ports are reserved but higher ports are used for 433 cores, count the reserved ports. This will allocate enough memory 434 in spin table to properly handle all cores. 435 436config EMC2305 437 bool "Fan controller" 438 help 439 Enable the EMC2305 fan controller for configuration of fan 440 speed. 441 442config NXP_ESBC 443 bool "NXP_ESBC" 444 help 445 Enable Freescale Secure Boot feature 446 447config QSPI_AHB_INIT 448 bool "Init the QSPI AHB bus" 449 help 450 The default setting for QSPI AHB bus just support 3bytes addressing. 451 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 452 bus for those flashes to support the full QSPI flash size. 453 454config FSPI_AHB_EN_4BYTE 455 bool "Enable 4-byte Fast Read command for AHB mode" 456 help 457 The default setting for FlexSPI AHB bus just supports 3-byte addressing. 458 But some FlexSPI flash sizes are up to 64MBytes. 459 This flag enables fast read command for AHB mode and modifies required 460 LUT to support full FlexSPI flash. 461 462config SYS_CCI400_OFFSET 463 hex "Offset for CCI400 base" 464 depends on SYS_FSL_HAS_CCI400 465 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A 466 default 0x180000 if FSL_LSCH2 467 help 468 Offset for CCI400 base 469 CCI400 base addr = CCSRBAR + CCI400_OFFSET 470 471config SYS_FSL_IFC_BANK_COUNT 472 int "Maximum banks of Integrated flash controller" 473 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 474 default 4 if ARCH_LS1043A 475 default 4 if ARCH_LS1046A 476 default 8 if ARCH_LS2080A || ARCH_LS1088A 477 478config SYS_FSL_HAS_CCI400 479 bool 480 481config SYS_FSL_HAS_CCN504 482 bool 483 484config SYS_FSL_HAS_CCN508 485 bool 486 487config SYS_FSL_HAS_DP_DDR 488 bool 489 490config SYS_FSL_SRDS_1 491 bool 492 493config SYS_FSL_SRDS_2 494 bool 495 496config SYS_NXP_SRDS_3 497 bool 498 499config SYS_HAS_SERDES 500 bool 501 502config FSL_TZASC_1 503 bool 504 505config FSL_TZASC_2 506 bool 507 508config FSL_TZASC_400 509 bool 510 511config FSL_TZPC_BP147 512 bool 513endmenu 514 515menu "Layerscape clock tree configuration" 516 depends on FSL_LSCH2 || FSL_LSCH3 517 518config SYS_FSL_CLK 519 bool "Enable clock tree initialization" 520 default y 521 522config CLUSTER_CLK_FREQ 523 int "Reference clock of core cluster" 524 depends on ARCH_LS1012A 525 default 100000000 526 help 527 This number is the reference clock frequency of core PLL. 528 For most platforms, the core PLL and Platform PLL have the same 529 reference clock, but for some platforms, LS1012A for instance, 530 they are provided sepatately. 531 532config SYS_FSL_PCLK_DIV 533 int "Platform clock divider" 534 default 1 if ARCH_LS1028A 535 default 1 if ARCH_LS1043A 536 default 1 if ARCH_LS1046A 537 default 1 if ARCH_LS1088A 538 default 2 539 help 540 This is the divider that is used to derive Platform clock from 541 Platform PLL, in another word: 542 Platform_clk = Platform_PLL_freq / this_divider 543 544config SYS_FSL_DSPI_CLK_DIV 545 int "DSPI clock divider" 546 default 1 if ARCH_LS1043A 547 default 2 548 help 549 This is the divider that is used to derive DSPI clock from Platform 550 clock, in another word DSPI_clk = Platform_clk / this_divider. 551 552config SYS_FSL_DUART_CLK_DIV 553 int "DUART clock divider" 554 default 1 if ARCH_LS1043A 555 default 4 if ARCH_LX2160A 556 default 4 if ARCH_LX2162A 557 default 2 558 help 559 This is the divider that is used to derive DUART clock from Platform 560 clock, in another word DUART_clk = Platform_clk / this_divider. 561 562config SYS_FSL_I2C_CLK_DIV 563 int "I2C clock divider" 564 default 1 if ARCH_LS1043A 565 default 4 if ARCH_LS1012A 566 default 4 if ARCH_LS1028A 567 default 8 if ARCH_LX2160A 568 default 8 if ARCH_LX2162A 569 default 8 if ARCH_LS1088A 570 default 2 571 help 572 This is the divider that is used to derive I2C clock from Platform 573 clock, in another word I2C_clk = Platform_clk / this_divider. 574 575config SYS_FSL_IFC_CLK_DIV 576 int "IFC clock divider" 577 default 1 if ARCH_LS1043A 578 default 4 if ARCH_LS1012A 579 default 4 if ARCH_LS1028A 580 default 8 if ARCH_LX2160A 581 default 8 if ARCH_LX2162A 582 default 8 if ARCH_LS1088A 583 default 2 584 help 585 This is the divider that is used to derive IFC clock from Platform 586 clock, in another word IFC_clk = Platform_clk / this_divider. 587 588config SYS_FSL_LPUART_CLK_DIV 589 int "LPUART clock divider" 590 default 1 if ARCH_LS1043A 591 default 2 592 help 593 This is the divider that is used to derive LPUART clock from Platform 594 clock, in another word LPUART_clk = Platform_clk / this_divider. 595 596config SYS_FSL_SDHC_CLK_DIV 597 int "SDHC clock divider" 598 default 1 if ARCH_LS1043A 599 default 1 if ARCH_LS1012A 600 default 2 601 help 602 This is the divider that is used to derive SDHC clock from Platform 603 clock, in another word SDHC_clk = Platform_clk / this_divider. 604 605config SYS_FSL_QMAN_CLK_DIV 606 int "QMAN clock divider" 607 default 1 if ARCH_LS1043A 608 default 2 609 help 610 This is the divider that is used to derive QMAN clock from Platform 611 clock, in another word QMAN_clk = Platform_clk / this_divider. 612endmenu 613 614config RESV_RAM 615 bool 616 help 617 Reserve memory from the top, tracked by gd->arch.resv_ram. This 618 reserved RAM can be used by special driver that resides in memory 619 after U-Boot exits. It's up to implementation to allocate and allow 620 access to this reserved memory. For example, the reserved RAM can 621 be at the high end of physical memory. The reserve RAM may be 622 excluded from memory bank(s) passed to OS, or marked as reserved. 623 624config SYS_FSL_EC1 625 bool 626 help 627 Ethernet controller 1, this is connected to 628 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs 629 Provides DPAA2 capabilities 630 631config SYS_FSL_EC2 632 bool 633 help 634 Ethernet controller 2, this is connected to 635 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs 636 Provides DPAA2 capabilities 637 638config SYS_FSL_ERRATUM_A008336 639 bool 640 641config SYS_FSL_ERRATUM_A008514 642 bool 643 644config SYS_FSL_ERRATUM_A008585 645 bool 646 647config SYS_FSL_ERRATUM_A008850 648 bool 649 650config SYS_FSL_ERRATUM_A009203 651 bool 652 653config SYS_FSL_ERRATUM_A009635 654 bool 655 656config SYS_FSL_ERRATUM_A009660 657 bool 658 659config SYS_FSL_ERRATUM_A050382 660 bool 661 662config SYS_FSL_HAS_RGMII 663 bool 664 depends on SYS_FSL_EC1 || SYS_FSL_EC2 665 666config SPL_LDSCRIPT 667 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 668 669config HAS_FSL_XHCI_USB 670 bool 671 help 672 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 673 pins, select it when the pins are assigned to USB. 674 675config SYS_FSL_BOOTROM_BASE 676 hex 677 depends on FSL_LSCH2 678 default 0 679 680config SYS_FSL_BOOTROM_SIZE 681 hex 682 depends on FSL_LSCH2 683 default 0x1000000 684