1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SOCRATES 20 bool "Support socrates" 21 select ARCH_MPC8544 22 23config TARGET_P3041DS 24 bool "Support P3041DS" 25 select PHYS_64BIT 26 select ARCH_P3041 27 select BOARD_LATE_INIT if CHAIN_OF_TRUST 28 imply CMD_SATA 29 imply PANIC_HANG 30 31config TARGET_P4080DS 32 bool "Support P4080DS" 33 select PHYS_64BIT 34 select ARCH_P4080 35 select BOARD_LATE_INIT if CHAIN_OF_TRUST 36 imply CMD_SATA 37 imply PANIC_HANG 38 39config TARGET_P5040DS 40 bool "Support P5040DS" 41 select PHYS_64BIT 42 select ARCH_P5040 43 select BOARD_LATE_INIT if CHAIN_OF_TRUST 44 imply CMD_SATA 45 imply PANIC_HANG 46 47config TARGET_MPC8548CDS 48 bool "Support MPC8548CDS" 49 select ARCH_MPC8548 50 select FSL_VIA 51 select SYS_CACHE_SHIFT_5 52 53config TARGET_P1010RDB_PA 54 bool "Support P1010RDB_PA" 55 select ARCH_P1010 56 select BOARD_LATE_INIT if CHAIN_OF_TRUST 57 select SUPPORT_SPL 58 select SUPPORT_TPL 59 imply CMD_EEPROM 60 imply CMD_SATA 61 imply PANIC_HANG 62 63config TARGET_P1010RDB_PB 64 bool "Support P1010RDB_PB" 65 select ARCH_P1010 66 select BOARD_LATE_INIT if CHAIN_OF_TRUST 67 select SUPPORT_SPL 68 select SUPPORT_TPL 69 imply CMD_EEPROM 70 imply CMD_SATA 71 imply PANIC_HANG 72 73config TARGET_P1020RDB_PC 74 bool "Support P1020RDB-PC" 75 select SUPPORT_SPL 76 select SUPPORT_TPL 77 select ARCH_P1020 78 imply CMD_EEPROM 79 imply CMD_SATA 80 imply PANIC_HANG 81 82config TARGET_P1020RDB_PD 83 bool "Support P1020RDB-PD" 84 select SUPPORT_SPL 85 select SUPPORT_TPL 86 select ARCH_P1020 87 imply CMD_EEPROM 88 imply CMD_SATA 89 imply PANIC_HANG 90 91config TARGET_P2020RDB 92 bool "Support P2020RDB-PC" 93 select SUPPORT_SPL 94 select SUPPORT_TPL 95 select ARCH_P2020 96 imply CMD_EEPROM 97 imply CMD_SATA 98 imply SATA_SIL 99 100config TARGET_P2041RDB 101 bool "Support P2041RDB" 102 select ARCH_P2041 103 select BOARD_LATE_INIT if CHAIN_OF_TRUST 104 select PHYS_64BIT 105 imply CMD_SATA 106 imply FSL_SATA 107 108config TARGET_QEMU_PPCE500 109 bool "Support qemu-ppce500" 110 select ARCH_QEMU_E500 111 select PHYS_64BIT 112 113config TARGET_T1024RDB 114 bool "Support T1024RDB" 115 select ARCH_T1024 116 select BOARD_LATE_INIT if CHAIN_OF_TRUST 117 select SUPPORT_SPL 118 select PHYS_64BIT 119 select FSL_DDR_INTERACTIVE 120 imply CMD_EEPROM 121 imply PANIC_HANG 122 123config TARGET_T1042RDB 124 bool "Support T1042RDB" 125 select ARCH_T1042 126 select BOARD_LATE_INIT if CHAIN_OF_TRUST 127 select SUPPORT_SPL 128 select PHYS_64BIT 129 130config TARGET_T1042D4RDB 131 bool "Support T1042D4RDB" 132 select ARCH_T1042 133 select BOARD_LATE_INIT if CHAIN_OF_TRUST 134 select SUPPORT_SPL 135 select PHYS_64BIT 136 imply PANIC_HANG 137 138config TARGET_T1042RDB_PI 139 bool "Support T1042RDB_PI" 140 select ARCH_T1042 141 select BOARD_LATE_INIT if CHAIN_OF_TRUST 142 select SUPPORT_SPL 143 select PHYS_64BIT 144 imply PANIC_HANG 145 146config TARGET_T2080QDS 147 bool "Support T2080QDS" 148 select ARCH_T2080 149 select BOARD_LATE_INIT if CHAIN_OF_TRUST 150 select SUPPORT_SPL 151 select PHYS_64BIT 152 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 153 select FSL_DDR_INTERACTIVE 154 imply CMD_SATA 155 156config TARGET_T2080RDB 157 bool "Support T2080RDB" 158 select ARCH_T2080 159 select BOARD_LATE_INIT if CHAIN_OF_TRUST 160 select SUPPORT_SPL 161 select PHYS_64BIT 162 imply CMD_SATA 163 imply PANIC_HANG 164 165config TARGET_T4240RDB 166 bool "Support T4240RDB" 167 select ARCH_T4240 168 select SUPPORT_SPL 169 select PHYS_64BIT 170 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 171 imply CMD_SATA 172 imply PANIC_HANG 173 174config TARGET_KMP204X 175 bool "Support kmp204x" 176 select VENDOR_KM 177 178config TARGET_KMCENT2 179 bool "Support kmcent2" 180 select VENDOR_KM 181 182endchoice 183 184config ARCH_B4420 185 bool 186 select E500MC 187 select E6500 188 select FSL_LAW 189 select SYS_FSL_DDR_VER_47 190 select SYS_FSL_ERRATUM_A004477 191 select SYS_FSL_ERRATUM_A005871 192 select SYS_FSL_ERRATUM_A006379 193 select SYS_FSL_ERRATUM_A006384 194 select SYS_FSL_ERRATUM_A006475 195 select SYS_FSL_ERRATUM_A006593 196 select SYS_FSL_ERRATUM_A007075 197 select SYS_FSL_ERRATUM_A007186 198 select SYS_FSL_ERRATUM_A007212 199 select SYS_FSL_ERRATUM_A009942 200 select SYS_FSL_HAS_DDR3 201 select SYS_FSL_HAS_SEC 202 select SYS_FSL_QORIQ_CHASSIS2 203 select SYS_FSL_SEC_BE 204 select SYS_FSL_SEC_COMPAT_4 205 select SYS_PPC64 206 select FSL_IFC 207 imply CMD_EEPROM 208 imply CMD_NAND 209 imply CMD_REGINFO 210 211config ARCH_B4860 212 bool 213 select E500MC 214 select E6500 215 select FSL_LAW 216 select SYS_FSL_DDR_VER_47 217 select SYS_FSL_ERRATUM_A004477 218 select SYS_FSL_ERRATUM_A005871 219 select SYS_FSL_ERRATUM_A006379 220 select SYS_FSL_ERRATUM_A006384 221 select SYS_FSL_ERRATUM_A006475 222 select SYS_FSL_ERRATUM_A006593 223 select SYS_FSL_ERRATUM_A007075 224 select SYS_FSL_ERRATUM_A007186 225 select SYS_FSL_ERRATUM_A007212 226 select SYS_FSL_ERRATUM_A007907 227 select SYS_FSL_ERRATUM_A009942 228 select SYS_FSL_HAS_DDR3 229 select SYS_FSL_HAS_SEC 230 select SYS_FSL_QORIQ_CHASSIS2 231 select SYS_FSL_SEC_BE 232 select SYS_FSL_SEC_COMPAT_4 233 select SYS_PPC64 234 select FSL_IFC 235 imply CMD_EEPROM 236 imply CMD_NAND 237 imply CMD_REGINFO 238 239config ARCH_BSC9131 240 bool 241 select FSL_LAW 242 select SYS_FSL_DDR_VER_44 243 select SYS_FSL_ERRATUM_A004477 244 select SYS_FSL_ERRATUM_A005125 245 select SYS_FSL_ERRATUM_ESDHC111 246 select SYS_FSL_HAS_DDR3 247 select SYS_FSL_HAS_SEC 248 select SYS_FSL_SEC_BE 249 select SYS_FSL_SEC_COMPAT_4 250 select FSL_IFC 251 imply CMD_EEPROM 252 imply CMD_NAND 253 imply CMD_REGINFO 254 255config ARCH_BSC9132 256 bool 257 select FSL_LAW 258 select SYS_FSL_DDR_VER_46 259 select SYS_FSL_ERRATUM_A004477 260 select SYS_FSL_ERRATUM_A005125 261 select SYS_FSL_ERRATUM_A005434 262 select SYS_FSL_ERRATUM_ESDHC111 263 select SYS_FSL_ERRATUM_I2C_A004447 264 select SYS_FSL_ERRATUM_IFC_A002769 265 select FSL_PCIE_RESET 266 select SYS_FSL_HAS_DDR3 267 select SYS_FSL_HAS_SEC 268 select SYS_FSL_SEC_BE 269 select SYS_FSL_SEC_COMPAT_4 270 select SYS_PPC_E500_USE_DEBUG_TLB 271 select FSL_IFC 272 imply CMD_EEPROM 273 imply CMD_MTDPARTS 274 imply CMD_NAND 275 imply CMD_PCI 276 imply CMD_REGINFO 277 278config ARCH_C29X 279 bool 280 select FSL_LAW 281 select SYS_FSL_DDR_VER_46 282 select SYS_FSL_ERRATUM_A005125 283 select SYS_FSL_ERRATUM_ESDHC111 284 select FSL_PCIE_RESET 285 select SYS_FSL_HAS_DDR3 286 select SYS_FSL_HAS_SEC 287 select SYS_FSL_SEC_BE 288 select SYS_FSL_SEC_COMPAT_6 289 select SYS_PPC_E500_USE_DEBUG_TLB 290 select FSL_IFC 291 imply CMD_NAND 292 imply CMD_PCI 293 imply CMD_REGINFO 294 295config ARCH_MPC8536 296 bool 297 select FSL_LAW 298 select SYS_FSL_ERRATUM_A004508 299 select SYS_FSL_ERRATUM_A005125 300 select FSL_PCIE_RESET 301 select SYS_FSL_HAS_DDR2 302 select SYS_FSL_HAS_DDR3 303 select SYS_FSL_HAS_SEC 304 select SYS_FSL_SEC_BE 305 select SYS_FSL_SEC_COMPAT_2 306 select SYS_PPC_E500_USE_DEBUG_TLB 307 select FSL_ELBC 308 imply CMD_NAND 309 imply CMD_SATA 310 imply CMD_REGINFO 311 312config ARCH_MPC8540 313 bool 314 select FSL_LAW 315 select SYS_FSL_HAS_DDR1 316 317config ARCH_MPC8544 318 bool 319 select FSL_LAW 320 select SYS_CACHE_SHIFT_5 321 select SYS_FSL_ERRATUM_A005125 322 select FSL_PCIE_RESET 323 select SYS_FSL_HAS_DDR2 324 select SYS_FSL_HAS_SEC 325 select SYS_FSL_SEC_BE 326 select SYS_FSL_SEC_COMPAT_2 327 select SYS_PPC_E500_USE_DEBUG_TLB 328 select FSL_ELBC 329 330config ARCH_MPC8548 331 bool 332 select FSL_LAW 333 select SYS_FSL_ERRATUM_A005125 334 select SYS_FSL_ERRATUM_NMG_DDR120 335 select SYS_FSL_ERRATUM_NMG_LBC103 336 select SYS_FSL_ERRATUM_NMG_ETSEC129 337 select SYS_FSL_ERRATUM_I2C_A004447 338 select FSL_PCIE_RESET 339 select SYS_FSL_HAS_DDR2 340 select SYS_FSL_HAS_DDR1 341 select SYS_FSL_HAS_SEC 342 select SYS_FSL_SEC_BE 343 select SYS_FSL_SEC_COMPAT_2 344 select SYS_PPC_E500_USE_DEBUG_TLB 345 imply CMD_REGINFO 346 347config ARCH_MPC8560 348 bool 349 select FSL_LAW 350 select SYS_FSL_HAS_DDR1 351 352config ARCH_P1010 353 bool 354 select FSL_LAW 355 select SYS_CACHE_SHIFT_5 356 select SYS_FSL_ERRATUM_A004477 357 select SYS_FSL_ERRATUM_A004508 358 select SYS_FSL_ERRATUM_A005125 359 select SYS_FSL_ERRATUM_A005275 360 select SYS_FSL_ERRATUM_A006261 361 select SYS_FSL_ERRATUM_A007075 362 select SYS_FSL_ERRATUM_ESDHC111 363 select SYS_FSL_ERRATUM_I2C_A004447 364 select SYS_FSL_ERRATUM_IFC_A002769 365 select SYS_FSL_ERRATUM_P1010_A003549 366 select SYS_FSL_ERRATUM_SEC_A003571 367 select SYS_FSL_ERRATUM_IFC_A003399 368 select FSL_PCIE_RESET 369 select SYS_FSL_HAS_DDR3 370 select SYS_FSL_HAS_SEC 371 select SYS_FSL_SEC_BE 372 select SYS_FSL_SEC_COMPAT_4 373 select SYS_PPC_E500_USE_DEBUG_TLB 374 select FSL_IFC 375 imply CMD_EEPROM 376 imply CMD_MTDPARTS 377 imply CMD_NAND 378 imply CMD_SATA 379 imply CMD_PCI 380 imply CMD_REGINFO 381 imply FSL_SATA 382 383config ARCH_P1011 384 bool 385 select FSL_LAW 386 select SYS_FSL_ERRATUM_A004508 387 select SYS_FSL_ERRATUM_A005125 388 select SYS_FSL_ERRATUM_ELBC_A001 389 select SYS_FSL_ERRATUM_ESDHC111 390 select FSL_PCIE_DISABLE_ASPM 391 select SYS_FSL_HAS_DDR3 392 select SYS_FSL_HAS_SEC 393 select SYS_FSL_SEC_BE 394 select SYS_FSL_SEC_COMPAT_2 395 select SYS_PPC_E500_USE_DEBUG_TLB 396 select FSL_ELBC 397 398config ARCH_P1020 399 bool 400 select FSL_LAW 401 select SYS_CACHE_SHIFT_5 402 select SYS_FSL_ERRATUM_A004508 403 select SYS_FSL_ERRATUM_A005125 404 select SYS_FSL_ERRATUM_ELBC_A001 405 select SYS_FSL_ERRATUM_ESDHC111 406 select FSL_PCIE_DISABLE_ASPM 407 select FSL_PCIE_RESET 408 select SYS_FSL_HAS_DDR3 409 select SYS_FSL_HAS_SEC 410 select SYS_FSL_SEC_BE 411 select SYS_FSL_SEC_COMPAT_2 412 select SYS_PPC_E500_USE_DEBUG_TLB 413 select FSL_ELBC 414 imply CMD_NAND 415 imply CMD_SATA 416 imply CMD_PCI 417 imply CMD_REGINFO 418 imply SATA_SIL 419 420config ARCH_P1021 421 bool 422 select FSL_LAW 423 select SYS_FSL_ERRATUM_A004508 424 select SYS_FSL_ERRATUM_A005125 425 select SYS_FSL_ERRATUM_ELBC_A001 426 select SYS_FSL_ERRATUM_ESDHC111 427 select FSL_PCIE_DISABLE_ASPM 428 select FSL_PCIE_RESET 429 select SYS_FSL_HAS_DDR3 430 select SYS_FSL_HAS_SEC 431 select SYS_FSL_SEC_BE 432 select SYS_FSL_SEC_COMPAT_2 433 select SYS_PPC_E500_USE_DEBUG_TLB 434 select FSL_ELBC 435 imply CMD_REGINFO 436 imply CMD_NAND 437 imply CMD_SATA 438 imply CMD_REGINFO 439 imply SATA_SIL 440 441config ARCH_P1023 442 bool 443 select FSL_LAW 444 select SYS_FSL_ERRATUM_A004508 445 select SYS_FSL_ERRATUM_A005125 446 select SYS_FSL_ERRATUM_I2C_A004447 447 select FSL_PCIE_RESET 448 select SYS_FSL_HAS_DDR3 449 select SYS_FSL_HAS_SEC 450 select SYS_FSL_SEC_BE 451 select SYS_FSL_SEC_COMPAT_4 452 select FSL_ELBC 453 454config ARCH_P1024 455 bool 456 select FSL_LAW 457 select SYS_FSL_ERRATUM_A004508 458 select SYS_FSL_ERRATUM_A005125 459 select SYS_FSL_ERRATUM_ELBC_A001 460 select SYS_FSL_ERRATUM_ESDHC111 461 select FSL_PCIE_DISABLE_ASPM 462 select FSL_PCIE_RESET 463 select SYS_FSL_HAS_DDR3 464 select SYS_FSL_HAS_SEC 465 select SYS_FSL_SEC_BE 466 select SYS_FSL_SEC_COMPAT_2 467 select SYS_PPC_E500_USE_DEBUG_TLB 468 select FSL_ELBC 469 imply CMD_EEPROM 470 imply CMD_NAND 471 imply CMD_SATA 472 imply CMD_PCI 473 imply CMD_REGINFO 474 imply SATA_SIL 475 476config ARCH_P1025 477 bool 478 select FSL_LAW 479 select SYS_FSL_ERRATUM_A004508 480 select SYS_FSL_ERRATUM_A005125 481 select SYS_FSL_ERRATUM_ELBC_A001 482 select SYS_FSL_ERRATUM_ESDHC111 483 select FSL_PCIE_DISABLE_ASPM 484 select FSL_PCIE_RESET 485 select SYS_FSL_HAS_DDR3 486 select SYS_FSL_HAS_SEC 487 select SYS_FSL_SEC_BE 488 select SYS_FSL_SEC_COMPAT_2 489 select SYS_PPC_E500_USE_DEBUG_TLB 490 select FSL_ELBC 491 imply CMD_SATA 492 imply CMD_REGINFO 493 494config ARCH_P2020 495 bool 496 select FSL_LAW 497 select SYS_CACHE_SHIFT_5 498 select SYS_FSL_ERRATUM_A004477 499 select SYS_FSL_ERRATUM_A004508 500 select SYS_FSL_ERRATUM_A005125 501 select SYS_FSL_ERRATUM_ESDHC111 502 select SYS_FSL_ERRATUM_ESDHC_A001 503 select FSL_PCIE_RESET 504 select SYS_FSL_HAS_DDR3 505 select SYS_FSL_HAS_SEC 506 select SYS_FSL_SEC_BE 507 select SYS_FSL_SEC_COMPAT_2 508 select SYS_PPC_E500_USE_DEBUG_TLB 509 select FSL_ELBC 510 imply CMD_EEPROM 511 imply CMD_NAND 512 imply CMD_REGINFO 513 514config ARCH_P2041 515 bool 516 select E500MC 517 select FSL_LAW 518 select SYS_CACHE_SHIFT_6 519 select SYS_FSL_ERRATUM_A004510 520 select SYS_FSL_ERRATUM_A004849 521 select SYS_FSL_ERRATUM_A005275 522 select SYS_FSL_ERRATUM_A006261 523 select SYS_FSL_ERRATUM_CPU_A003999 524 select SYS_FSL_ERRATUM_DDR_A003 525 select SYS_FSL_ERRATUM_DDR_A003474 526 select SYS_FSL_ERRATUM_ESDHC111 527 select SYS_FSL_ERRATUM_I2C_A004447 528 select SYS_FSL_ERRATUM_NMG_CPU_A011 529 select SYS_FSL_ERRATUM_SRIO_A004034 530 select SYS_FSL_ERRATUM_USB14 531 select SYS_FSL_HAS_DDR3 532 select SYS_FSL_HAS_SEC 533 select SYS_FSL_QORIQ_CHASSIS1 534 select SYS_FSL_SEC_BE 535 select SYS_FSL_SEC_COMPAT_4 536 select FSL_ELBC 537 imply CMD_NAND 538 539config ARCH_P3041 540 bool 541 select E500MC 542 select FSL_LAW 543 select SYS_CACHE_SHIFT_6 544 select SYS_FSL_DDR_VER_44 545 select SYS_FSL_ERRATUM_A004510 546 select SYS_FSL_ERRATUM_A004849 547 select SYS_FSL_ERRATUM_A005275 548 select SYS_FSL_ERRATUM_A005812 549 select SYS_FSL_ERRATUM_A006261 550 select SYS_FSL_ERRATUM_CPU_A003999 551 select SYS_FSL_ERRATUM_DDR_A003 552 select SYS_FSL_ERRATUM_DDR_A003474 553 select SYS_FSL_ERRATUM_ESDHC111 554 select SYS_FSL_ERRATUM_I2C_A004447 555 select SYS_FSL_ERRATUM_NMG_CPU_A011 556 select SYS_FSL_ERRATUM_SRIO_A004034 557 select SYS_FSL_ERRATUM_USB14 558 select SYS_FSL_HAS_DDR3 559 select SYS_FSL_HAS_SEC 560 select SYS_FSL_QORIQ_CHASSIS1 561 select SYS_FSL_SEC_BE 562 select SYS_FSL_SEC_COMPAT_4 563 select FSL_ELBC 564 imply CMD_NAND 565 imply CMD_SATA 566 imply CMD_REGINFO 567 imply FSL_SATA 568 569config ARCH_P4080 570 bool 571 select E500MC 572 select FSL_LAW 573 select SYS_CACHE_SHIFT_6 574 select SYS_FSL_DDR_VER_44 575 select SYS_FSL_ERRATUM_A004510 576 select SYS_FSL_ERRATUM_A004580 577 select SYS_FSL_ERRATUM_A004849 578 select SYS_FSL_ERRATUM_A005812 579 select SYS_FSL_ERRATUM_A007075 580 select SYS_FSL_ERRATUM_CPC_A002 581 select SYS_FSL_ERRATUM_CPC_A003 582 select SYS_FSL_ERRATUM_CPU_A003999 583 select SYS_FSL_ERRATUM_DDR_A003 584 select SYS_FSL_ERRATUM_DDR_A003474 585 select SYS_FSL_ERRATUM_ELBC_A001 586 select SYS_FSL_ERRATUM_ESDHC111 587 select SYS_FSL_ERRATUM_ESDHC13 588 select SYS_FSL_ERRATUM_ESDHC135 589 select SYS_FSL_ERRATUM_I2C_A004447 590 select SYS_FSL_ERRATUM_NMG_CPU_A011 591 select SYS_FSL_ERRATUM_SRIO_A004034 592 select SYS_P4080_ERRATUM_CPU22 593 select SYS_P4080_ERRATUM_PCIE_A003 594 select SYS_P4080_ERRATUM_SERDES8 595 select SYS_P4080_ERRATUM_SERDES9 596 select SYS_P4080_ERRATUM_SERDES_A001 597 select SYS_P4080_ERRATUM_SERDES_A005 598 select SYS_FSL_HAS_DDR3 599 select SYS_FSL_HAS_SEC 600 select SYS_FSL_QORIQ_CHASSIS1 601 select SYS_FSL_SEC_BE 602 select SYS_FSL_SEC_COMPAT_4 603 select FSL_ELBC 604 imply CMD_SATA 605 imply CMD_REGINFO 606 imply SATA_SIL 607 608config ARCH_P5040 609 bool 610 select E500MC 611 select FSL_LAW 612 select SYS_CACHE_SHIFT_6 613 select SYS_FSL_DDR_VER_44 614 select SYS_FSL_ERRATUM_A004510 615 select SYS_FSL_ERRATUM_A004699 616 select SYS_FSL_ERRATUM_A005275 617 select SYS_FSL_ERRATUM_A005812 618 select SYS_FSL_ERRATUM_A006261 619 select SYS_FSL_ERRATUM_DDR_A003 620 select SYS_FSL_ERRATUM_DDR_A003474 621 select SYS_FSL_ERRATUM_ESDHC111 622 select SYS_FSL_ERRATUM_USB14 623 select SYS_FSL_HAS_DDR3 624 select SYS_FSL_HAS_SEC 625 select SYS_FSL_QORIQ_CHASSIS1 626 select SYS_FSL_SEC_BE 627 select SYS_FSL_SEC_COMPAT_4 628 select SYS_PPC64 629 select FSL_ELBC 630 imply CMD_SATA 631 imply CMD_REGINFO 632 imply FSL_SATA 633 634config ARCH_QEMU_E500 635 bool 636 select SYS_CACHE_SHIFT_5 637 638config ARCH_T1024 639 bool 640 select E500MC 641 select FSL_LAW 642 select SYS_CACHE_SHIFT_6 643 select SYS_FSL_DDR_VER_50 644 select SYS_FSL_ERRATUM_A008378 645 select SYS_FSL_ERRATUM_A008109 646 select SYS_FSL_ERRATUM_A009663 647 select SYS_FSL_ERRATUM_A009942 648 select SYS_FSL_ERRATUM_ESDHC111 649 select SYS_FSL_HAS_DDR3 650 select SYS_FSL_HAS_DDR4 651 select SYS_FSL_HAS_SEC 652 select SYS_FSL_QORIQ_CHASSIS2 653 select SYS_FSL_SEC_BE 654 select SYS_FSL_SEC_COMPAT_5 655 select FSL_IFC 656 imply CMD_EEPROM 657 imply CMD_NAND 658 imply CMD_MTDPARTS 659 imply CMD_REGINFO 660 661config ARCH_T1040 662 bool 663 select E500MC 664 select FSL_LAW 665 select SYS_CACHE_SHIFT_6 666 select SYS_FSL_DDR_VER_50 667 select SYS_FSL_ERRATUM_A008044 668 select SYS_FSL_ERRATUM_A008378 669 select SYS_FSL_ERRATUM_A008109 670 select SYS_FSL_ERRATUM_A009663 671 select SYS_FSL_ERRATUM_A009942 672 select SYS_FSL_ERRATUM_ESDHC111 673 select SYS_FSL_HAS_DDR3 674 select SYS_FSL_HAS_DDR4 675 select SYS_FSL_HAS_SEC 676 select SYS_FSL_QORIQ_CHASSIS2 677 select SYS_FSL_SEC_BE 678 select SYS_FSL_SEC_COMPAT_5 679 select FSL_IFC 680 imply CMD_MTDPARTS 681 imply CMD_NAND 682 imply CMD_REGINFO 683 684config ARCH_T1042 685 bool 686 select E500MC 687 select FSL_LAW 688 select SYS_CACHE_SHIFT_6 689 select SYS_FSL_DDR_VER_50 690 select SYS_FSL_ERRATUM_A008044 691 select SYS_FSL_ERRATUM_A008378 692 select SYS_FSL_ERRATUM_A008109 693 select SYS_FSL_ERRATUM_A009663 694 select SYS_FSL_ERRATUM_A009942 695 select SYS_FSL_ERRATUM_ESDHC111 696 select SYS_FSL_HAS_DDR3 697 select SYS_FSL_HAS_DDR4 698 select SYS_FSL_HAS_SEC 699 select SYS_FSL_QORIQ_CHASSIS2 700 select SYS_FSL_SEC_BE 701 select SYS_FSL_SEC_COMPAT_5 702 select FSL_IFC 703 imply CMD_MTDPARTS 704 imply CMD_NAND 705 imply CMD_REGINFO 706 707config ARCH_T2080 708 bool 709 select E500MC 710 select E6500 711 select FSL_LAW 712 select SYS_CACHE_SHIFT_6 713 select SYS_FSL_DDR_VER_47 714 select SYS_FSL_ERRATUM_A006379 715 select SYS_FSL_ERRATUM_A006593 716 select SYS_FSL_ERRATUM_A007186 717 select SYS_FSL_ERRATUM_A007212 718 select SYS_FSL_ERRATUM_A007815 719 select SYS_FSL_ERRATUM_A007907 720 select SYS_FSL_ERRATUM_A008109 721 select SYS_FSL_ERRATUM_A009942 722 select SYS_FSL_ERRATUM_ESDHC111 723 select FSL_PCIE_RESET 724 select SYS_FSL_HAS_DDR3 725 select SYS_FSL_HAS_SEC 726 select SYS_FSL_QORIQ_CHASSIS2 727 select SYS_FSL_SEC_BE 728 select SYS_FSL_SEC_COMPAT_4 729 select SYS_PPC64 730 select FSL_IFC 731 imply CMD_SATA 732 imply CMD_NAND 733 imply CMD_REGINFO 734 imply FSL_SATA 735 imply ID_EEPROM 736 737config ARCH_T4240 738 bool 739 select E500MC 740 select E6500 741 select FSL_LAW 742 select SYS_CACHE_SHIFT_6 743 select SYS_FSL_DDR_VER_47 744 select SYS_FSL_ERRATUM_A004468 745 select SYS_FSL_ERRATUM_A005871 746 select SYS_FSL_ERRATUM_A006261 747 select SYS_FSL_ERRATUM_A006379 748 select SYS_FSL_ERRATUM_A006593 749 select SYS_FSL_ERRATUM_A007186 750 select SYS_FSL_ERRATUM_A007798 751 select SYS_FSL_ERRATUM_A007815 752 select SYS_FSL_ERRATUM_A007907 753 select SYS_FSL_ERRATUM_A008109 754 select SYS_FSL_ERRATUM_A009942 755 select SYS_FSL_HAS_DDR3 756 select SYS_FSL_HAS_SEC 757 select SYS_FSL_QORIQ_CHASSIS2 758 select SYS_FSL_SEC_BE 759 select SYS_FSL_SEC_COMPAT_4 760 select SYS_PPC64 761 select FSL_IFC 762 imply CMD_SATA 763 imply CMD_NAND 764 imply CMD_REGINFO 765 imply FSL_SATA 766 767config MPC85XX_HAVE_RESET_VECTOR 768 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" 769 depends on MPC85xx 770 771config BOOKE 772 bool 773 default y 774 775config E500 776 bool 777 default y 778 help 779 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 780 781config E500MC 782 bool 783 imply CMD_PCI 784 help 785 Enble PowerPC E500MC core 786 787config E6500 788 bool 789 help 790 Enable PowerPC E6500 core 791 792config FSL_LAW 793 bool 794 help 795 Use Freescale common code for Local Access Window 796 797config NXP_ESBC 798 bool "NXP_ESBC" 799 help 800 Enable Freescale Secure Boot feature. Normally selected 801 by defconfig. If unsure, do not change. 802 803config MAX_CPUS 804 int "Maximum number of CPUs permitted for MPC85xx" 805 default 12 if ARCH_T4240 806 default 8 if ARCH_P4080 807 default 4 if ARCH_B4860 || \ 808 ARCH_P2041 || \ 809 ARCH_P3041 || \ 810 ARCH_P5040 || \ 811 ARCH_T1040 || \ 812 ARCH_T1042 || \ 813 ARCH_T2080 814 default 2 if ARCH_B4420 || \ 815 ARCH_BSC9132 || \ 816 ARCH_P1020 || \ 817 ARCH_P1021 || \ 818 ARCH_P1023 || \ 819 ARCH_P1024 || \ 820 ARCH_P1025 || \ 821 ARCH_P2020 || \ 822 ARCH_T1024 823 default 1 824 help 825 Set this number to the maximum number of possible CPUs in the SoC. 826 SoCs may have multiple clusters with each cluster may have multiple 827 ports. If some ports are reserved but higher ports are used for 828 cores, count the reserved ports. This will allocate enough memory 829 in spin table to properly handle all cores. 830 831config SYS_CCSRBAR_DEFAULT 832 hex "Default CCSRBAR address" 833 default 0xff700000 if ARCH_BSC9131 || \ 834 ARCH_BSC9132 || \ 835 ARCH_C29X || \ 836 ARCH_MPC8536 || \ 837 ARCH_MPC8540 || \ 838 ARCH_MPC8544 || \ 839 ARCH_MPC8548 || \ 840 ARCH_MPC8560 || \ 841 ARCH_P1010 || \ 842 ARCH_P1011 || \ 843 ARCH_P1020 || \ 844 ARCH_P1021 || \ 845 ARCH_P1024 || \ 846 ARCH_P1025 || \ 847 ARCH_P2020 848 default 0xff600000 if ARCH_P1023 849 default 0xfe000000 if ARCH_B4420 || \ 850 ARCH_B4860 || \ 851 ARCH_P2041 || \ 852 ARCH_P3041 || \ 853 ARCH_P4080 || \ 854 ARCH_P5040 || \ 855 ARCH_T1024 || \ 856 ARCH_T1040 || \ 857 ARCH_T1042 || \ 858 ARCH_T2080 || \ 859 ARCH_T4240 860 default 0xe0000000 if ARCH_QEMU_E500 861 help 862 Default value of CCSRBAR comes from power-on-reset. It 863 is fixed on each SoC. Some SoCs can have different value 864 if changed by pre-boot regime. The value here must match 865 the current value in SoC. If not sure, do not change. 866 867config SYS_FSL_ERRATUM_A004468 868 bool 869 870config SYS_FSL_ERRATUM_A004477 871 bool 872 873config SYS_FSL_ERRATUM_A004508 874 bool 875 876config SYS_FSL_ERRATUM_A004580 877 bool 878 879config SYS_FSL_ERRATUM_A004699 880 bool 881 882config SYS_FSL_ERRATUM_A004849 883 bool 884 885config SYS_FSL_ERRATUM_A004510 886 bool 887 888config SYS_FSL_ERRATUM_A004510_SVR_REV 889 hex 890 depends on SYS_FSL_ERRATUM_A004510 891 default 0x20 if ARCH_P4080 892 default 0x10 893 894config SYS_FSL_ERRATUM_A004510_SVR_REV2 895 hex 896 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 897 default 0x11 898 899config SYS_FSL_ERRATUM_A005125 900 bool 901 902config SYS_FSL_ERRATUM_A005434 903 bool 904 905config SYS_FSL_ERRATUM_A005812 906 bool 907 908config SYS_FSL_ERRATUM_A005871 909 bool 910 911config SYS_FSL_ERRATUM_A005275 912 bool 913 914config SYS_FSL_ERRATUM_A006261 915 bool 916 917config SYS_FSL_ERRATUM_A006379 918 bool 919 920config SYS_FSL_ERRATUM_A006384 921 bool 922 923config SYS_FSL_ERRATUM_A006475 924 bool 925 926config SYS_FSL_ERRATUM_A006593 927 bool 928 929config SYS_FSL_ERRATUM_A007075 930 bool 931 932config SYS_FSL_ERRATUM_A007186 933 bool 934 935config SYS_FSL_ERRATUM_A007212 936 bool 937 938config SYS_FSL_ERRATUM_A007815 939 bool 940 941config SYS_FSL_ERRATUM_A007798 942 bool 943 944config SYS_FSL_ERRATUM_A007907 945 bool 946 947config SYS_FSL_ERRATUM_A008044 948 bool 949 950config SYS_FSL_ERRATUM_CPC_A002 951 bool 952 953config SYS_FSL_ERRATUM_CPC_A003 954 bool 955 956config SYS_FSL_ERRATUM_CPU_A003999 957 bool 958 959config SYS_FSL_ERRATUM_ELBC_A001 960 bool 961 962config SYS_FSL_ERRATUM_I2C_A004447 963 bool 964 965config SYS_FSL_A004447_SVR_REV 966 hex 967 depends on SYS_FSL_ERRATUM_I2C_A004447 968 default 0x00 if ARCH_MPC8548 969 default 0x10 if ARCH_P1010 970 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 971 default 0x20 if ARCH_P3041 || ARCH_P4080 972 973config SYS_FSL_ERRATUM_IFC_A002769 974 bool 975 976config SYS_FSL_ERRATUM_IFC_A003399 977 bool 978 979config SYS_FSL_ERRATUM_NMG_CPU_A011 980 bool 981 982config SYS_FSL_ERRATUM_NMG_ETSEC129 983 bool 984 985config SYS_FSL_ERRATUM_NMG_LBC103 986 bool 987 988config SYS_FSL_ERRATUM_P1010_A003549 989 bool 990 991config SYS_FSL_ERRATUM_SATA_A001 992 bool 993 994config SYS_FSL_ERRATUM_SEC_A003571 995 bool 996 997config SYS_FSL_ERRATUM_SRIO_A004034 998 bool 999 1000config SYS_FSL_ERRATUM_USB14 1001 bool 1002 1003config SYS_P4080_ERRATUM_CPU22 1004 bool 1005 1006config SYS_P4080_ERRATUM_PCIE_A003 1007 bool 1008 1009config SYS_P4080_ERRATUM_SERDES8 1010 bool 1011 1012config SYS_P4080_ERRATUM_SERDES9 1013 bool 1014 1015config SYS_P4080_ERRATUM_SERDES_A001 1016 bool 1017 1018config SYS_P4080_ERRATUM_SERDES_A005 1019 bool 1020 1021config FSL_PCIE_DISABLE_ASPM 1022 bool 1023 1024config FSL_PCIE_RESET 1025 bool 1026 1027config SYS_FSL_QORIQ_CHASSIS1 1028 bool 1029 1030config SYS_FSL_QORIQ_CHASSIS2 1031 bool 1032 1033config SYS_FSL_NUM_LAWS 1034 int "Number of local access windows" 1035 depends on FSL_LAW 1036 default 32 if ARCH_B4420 || \ 1037 ARCH_B4860 || \ 1038 ARCH_P2041 || \ 1039 ARCH_P3041 || \ 1040 ARCH_P4080 || \ 1041 ARCH_P5040 || \ 1042 ARCH_T2080 || \ 1043 ARCH_T4240 1044 default 16 if ARCH_T1024 || \ 1045 ARCH_T1040 || \ 1046 ARCH_T1042 1047 default 12 if ARCH_BSC9131 || \ 1048 ARCH_BSC9132 || \ 1049 ARCH_C29X || \ 1050 ARCH_MPC8536 || \ 1051 ARCH_P1010 || \ 1052 ARCH_P1011 || \ 1053 ARCH_P1020 || \ 1054 ARCH_P1021 || \ 1055 ARCH_P1023 || \ 1056 ARCH_P1024 || \ 1057 ARCH_P1025 || \ 1058 ARCH_P2020 1059 default 10 if ARCH_MPC8544 || \ 1060 ARCH_MPC8548 1061 default 8 if ARCH_MPC8540 || \ 1062 ARCH_MPC8560 1063 help 1064 Number of local access windows. This is fixed per SoC. 1065 If not sure, do not change. 1066 1067config SYS_FSL_THREADS_PER_CORE 1068 int 1069 default 2 if E6500 1070 default 1 1071 1072config SYS_NUM_TLBCAMS 1073 int "Number of TLB CAM entries" 1074 default 64 if E500MC 1075 default 16 1076 help 1077 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1078 16 for other E500 SoCs. 1079 1080config SYS_PPC64 1081 bool 1082 1083config SYS_PPC_E500_USE_DEBUG_TLB 1084 bool 1085 1086config FSL_IFC 1087 bool 1088 1089config FSL_ELBC 1090 bool 1091 1092config SYS_PPC_E500_DEBUG_TLB 1093 int "Temporary TLB entry for external debugger" 1094 depends on SYS_PPC_E500_USE_DEBUG_TLB 1095 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1096 default 1 if ARCH_MPC8536 1097 default 2 if ARCH_P1011 || \ 1098 ARCH_P1020 || \ 1099 ARCH_P1021 || \ 1100 ARCH_P1024 || \ 1101 ARCH_P1025 || \ 1102 ARCH_P2020 1103 default 3 if ARCH_P1010 || \ 1104 ARCH_BSC9132 || \ 1105 ARCH_C29X 1106 help 1107 Select a temporary TLB entry to be used during boot to work 1108 around limitations in e500v1 and e500v2 external debugger 1109 support. This reduces the portions of the boot code where 1110 breakpoints and single stepping do not work. The value of this 1111 symbol should be set to the TLB1 entry to be used for this 1112 purpose. If unsure, do not change. 1113 1114config SYS_FSL_IFC_CLK_DIV 1115 int "Divider of platform clock" 1116 depends on FSL_IFC 1117 default 2 if ARCH_B4420 || \ 1118 ARCH_B4860 || \ 1119 ARCH_T1024 || \ 1120 ARCH_T1040 || \ 1121 ARCH_T1042 || \ 1122 ARCH_T4240 1123 default 1 1124 help 1125 Defines divider of platform clock(clock input to 1126 IFC controller). 1127 1128config SYS_FSL_LBC_CLK_DIV 1129 int "Divider of platform clock" 1130 depends on FSL_ELBC || ARCH_MPC8540 || \ 1131 ARCH_MPC8548 || \ 1132 ARCH_MPC8560 1133 1134 default 2 if ARCH_P2041 || \ 1135 ARCH_P3041 || \ 1136 ARCH_P4080 || \ 1137 ARCH_P5040 1138 default 1 1139 1140 help 1141 Defines divider of platform clock(clock input to 1142 eLBC controller). 1143 1144config FSL_VIA 1145 bool 1146 1147source "board/emulation/qemu-ppce500/Kconfig" 1148source "board/freescale/corenet_ds/Kconfig" 1149source "board/freescale/mpc8548cds/Kconfig" 1150source "board/freescale/p1010rdb/Kconfig" 1151source "board/freescale/p1_p2_rdb_pc/Kconfig" 1152source "board/freescale/p2041rdb/Kconfig" 1153source "board/freescale/t102xrdb/Kconfig" 1154source "board/freescale/t104xrdb/Kconfig" 1155source "board/freescale/t208xqds/Kconfig" 1156source "board/freescale/t208xrdb/Kconfig" 1157source "board/freescale/t4rdb/Kconfig" 1158source "board/keymile/Kconfig" 1159source "board/socrates/Kconfig" 1160 1161endmenu 1162