1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao@motorola.com> 6 */ 7 8 /* 9 * mpc8560ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc. in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #include <linux/delay.h> 21 22 /* High Level Configuration Options */ 23 #define CONFIG_CPM2 1 /* has CPM2 */ 24 25 /* 26 * default CCARBAR is at 0xff700000 27 * assume U-Boot is less than 0.5MB 28 */ 29 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 32 33 /* 34 * sysclk for MPC85xx 35 * 36 * Two valid values are: 37 * 33000000 38 * 66000000 39 * 40 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 41 * is likely the desired value here, so that is now the default. 42 * The board, however, can run at 66MHz. In any event, this value 43 * must match the settings of some switches. Details can be found 44 * in the README.mpc85xxads. 45 */ 46 47 #ifndef CONFIG_SYS_CLK_FREQ 48 #define CONFIG_SYS_CLK_FREQ 33000000 49 #endif 50 51 /* 52 * These can be toggled for performance analysis, otherwise use default. 53 */ 54 #define CONFIG_L2_CACHE /* toggle L2 cache */ 55 #define CONFIG_BTB /* toggle branch predition */ 56 57 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 58 59 #define CONFIG_SYS_CCSRBAR 0xe0000000 60 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 61 62 /* DDR Setup */ 63 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 64 65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 66 67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 69 70 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 71 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 72 73 /* I2C addresses of SPD EEPROMs */ 74 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 75 76 /* These are used when DDR doesn't use SPD. */ 77 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 78 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 79 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 80 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 81 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 82 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 83 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 84 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 85 86 /* 87 * SDRAM on the Local Bus 88 */ 89 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 90 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 91 92 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 93 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 94 95 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 96 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 97 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 98 #undef CONFIG_SYS_FLASH_CHECKSUM 99 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 100 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 101 102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 103 104 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 105 #define CONFIG_SYS_RAMBOOT 106 #else 107 #undef CONFIG_SYS_RAMBOOT 108 #endif 109 110 #define CONFIG_SYS_FLASH_EMPTY_INFO 111 112 /* 113 * Local Bus Definitions 114 */ 115 116 /* 117 * Base Register 2 and Option Register 2 configure SDRAM. 118 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 119 * 120 * For BR2, need: 121 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 122 * port-size = 32-bits = BR2[19:20] = 11 123 * no parity checking = BR2[21:22] = 00 124 * SDRAM for MSEL = BR2[24:26] = 011 125 * Valid = BR[31] = 1 126 * 127 * 0 4 8 12 16 20 24 28 128 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 129 * 130 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 131 * FIXME: the top 17 bits of BR2. 132 */ 133 134 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 135 136 /* 137 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 138 * 139 * For OR2, need: 140 * 64MB mask for AM, OR2[0:7] = 1111 1100 141 * XAM, OR2[17:18] = 11 142 * 9 columns OR2[19-21] = 010 143 * 13 rows OR2[23-25] = 100 144 * EAD set for extra time OR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 148 */ 149 150 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 151 152 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 153 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 154 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 155 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 156 157 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 158 | LSDMR_RFCR5 \ 159 | LSDMR_PRETOACT3 \ 160 | LSDMR_ACTTORW3 \ 161 | LSDMR_BL8 \ 162 | LSDMR_WRC2 \ 163 | LSDMR_CL3 \ 164 | LSDMR_RFEN \ 165 ) 166 167 /* 168 * SDRAM Controller configuration sequence. 169 */ 170 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 171 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 172 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 173 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 174 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 175 176 /* 177 * 32KB, 8-bit wide for ADS config reg 178 */ 179 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 180 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 181 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 182 183 #define CONFIG_SYS_INIT_RAM_LOCK 1 184 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 185 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 186 187 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 191 192 /* Serial Port */ 193 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 194 195 #define CONFIG_SYS_BAUDRATE_TABLE \ 196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 197 198 /* 199 * I2C 200 */ 201 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 202 203 /* RapidIO MMU */ 204 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 205 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 206 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 207 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 208 209 /* 210 * General PCI 211 * Memory space is mapped 1-1, but I/O space must start from 0. 212 */ 213 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 214 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 215 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 216 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 217 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 218 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 219 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 220 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 221 222 #if defined(CONFIG_PCI) 223 224 #if !defined(CONFIG_PCI_PNP) 225 #define PCI_ENET0_IOADDR 0xe0000000 226 #define PCI_ENET0_MEMADDR 0xe0000000 227 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 228 #endif 229 230 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 231 232 #endif /* CONFIG_PCI */ 233 234 #ifdef CONFIG_TSEC_ENET 235 236 #define CONFIG_TSEC1 1 237 #define CONFIG_TSEC1_NAME "TSEC0" 238 #define CONFIG_TSEC2 1 239 #define CONFIG_TSEC2_NAME "TSEC1" 240 #define TSEC1_PHY_ADDR 0 241 #define TSEC2_PHY_ADDR 1 242 #define TSEC1_PHYIDX 0 243 #define TSEC2_PHYIDX 0 244 #define TSEC1_FLAGS TSEC_GIGABIT 245 #define TSEC2_FLAGS TSEC_GIGABIT 246 247 /* Options are: TSEC[0-1] */ 248 #define CONFIG_ETHPRIME "TSEC0" 249 250 #endif /* CONFIG_TSEC_ENET */ 251 252 /* 253 * Environment 254 */ 255 256 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 257 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 258 259 /* 260 * BOOTP options 261 */ 262 #define CONFIG_BOOTP_BOOTFILESIZE 263 264 #undef CONFIG_WATCHDOG /* watchdog disabled */ 265 266 /* 267 * Miscellaneous configurable options 268 */ 269 270 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 271 272 /* 273 * For booting Linux, the board info and command line data 274 * have to be in the first 64 MB of memory, since this is 275 * the maximum mapped by the Linux kernel during initialization. 276 */ 277 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 278 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 279 280 /* 281 * Environment Configuration 282 */ 283 #if defined(CONFIG_TSEC_ENET) 284 #define CONFIG_HAS_ETH0 285 #define CONFIG_HAS_ETH1 286 #define CONFIG_HAS_ETH2 287 #define CONFIG_HAS_ETH3 288 #endif 289 290 #define CONFIG_IPADDR 192.168.1.253 291 292 #define CONFIG_HOSTNAME "unknown" 293 #define CONFIG_ROOTPATH "/nfsroot" 294 #define CONFIG_BOOTFILE "your.uImage" 295 296 #define CONFIG_SERVERIP 192.168.1.1 297 #define CONFIG_GATEWAYIP 192.168.1.1 298 #define CONFIG_NETMASK 255.255.255.0 299 300 #define CONFIG_EXTRA_ENV_SETTINGS \ 301 "netdev=eth0\0" \ 302 "consoledev=ttyCPM\0" \ 303 "ramdiskaddr=1000000\0" \ 304 "ramdiskfile=your.ramdisk.u-boot\0" \ 305 "fdtaddr=400000\0" \ 306 "fdtfile=mpc8560ads.dtb\0" 307 308 #define NFSBOOTCOMMAND \ 309 "setenv bootargs root=/dev/nfs rw " \ 310 "nfsroot=$serverip:$rootpath " \ 311 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 312 "console=$consoledev,$baudrate $othbootargs;" \ 313 "tftp $loadaddr $bootfile;" \ 314 "tftp $fdtaddr $fdtfile;" \ 315 "bootm $loadaddr - $fdtaddr" 316 317 #define RAMBOOTCOMMAND \ 318 "setenv bootargs root=/dev/ram rw " \ 319 "console=$consoledev,$baudrate $othbootargs;" \ 320 "tftp $ramdiskaddr $ramdiskfile;" \ 321 "tftp $loadaddr $bootfile;" \ 322 "tftp $fdtaddr $fdtfile;" \ 323 "bootm $loadaddr $ramdiskaddr $fdtaddr" 324 325 #define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND 326 327 #endif /* __CONFIG_H */ 328