1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright (C) 2014 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 12 #include <asm/arch/stream_id_lsch3.h> 13 #include <asm/arch/config.h> 14 15 /* Link Definitions */ 16 #ifdef CONFIG_TFABOOT 17 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 18 #else 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 20 #endif 21 22 /* We need architecture specific misc initializations */ 23 24 /* Link Definitions */ 25 26 #ifndef CONFIG_SYS_FSL_DDR4 27 #define CONFIG_SYS_DDR_RAW_TIMING 28 #endif 29 30 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 31 32 #define CONFIG_VERY_BIG_RAM 33 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 34 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 35 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 36 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 37 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 38 39 /* 40 * SMP Definitinos 41 */ 42 #define CPU_RELEASE_ADDR secondary_boot_addr 43 44 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 45 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 46 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 47 /* 48 * DDR controller use 0 as the base address for binding. 49 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 50 */ 51 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 52 #define CONFIG_DP_DDR_CTRL 2 53 #define CONFIG_DP_DDR_NUM_CTRLS 1 54 #endif 55 56 /* Generic Timer Definitions */ 57 /* 58 * This is not an accurate number. It is used in start.S. The frequency 59 * will be udpated later when get_bus_freq(0) is available. 60 */ 61 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 62 63 /* GPIO */ 64 #ifdef CONFIG_DM_GPIO 65 #ifndef CONFIG_MPC8XXX_GPIO 66 #define CONFIG_MPC8XXX_GPIO 67 #endif 68 #endif 69 70 /* I2C */ 71 72 /* Serial Port */ 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE 1 75 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 76 77 /* IFC */ 78 #define CONFIG_FSL_IFC 79 80 /* 81 * During booting, IFC is mapped at the region of 0x30000000. 82 * But this region is limited to 256MB. To accommodate NOR, promjet 83 * and FPGA. This region is divided as below: 84 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 85 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 86 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 87 * 88 * To accommodate bigger NOR flash and other devices, we will map IFC 89 * chip selects to as below: 90 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 91 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 92 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 93 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 94 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 95 * 96 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 97 * CONFIG_SYS_FLASH_BASE has the final address (core view) 98 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 99 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 100 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 101 */ 102 103 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 104 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 105 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 106 107 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 108 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 109 110 #ifndef __ASSEMBLY__ 111 unsigned long long get_qixis_addr(void); 112 #endif 113 #define QIXIS_BASE get_qixis_addr() 114 #define QIXIS_BASE_PHYS 0x20000000 115 #define QIXIS_BASE_PHYS_EARLY 0xC000000 116 #define QIXIS_STAT_PRES1 0xb 117 #define QIXIS_SDID_MASK 0x07 118 #define QIXIS_ESDHC_NO_ADAPTER 0x7 119 120 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 121 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 122 123 /* MC firmware */ 124 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 125 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 126 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 127 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 128 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 129 /* For LS2085A */ 130 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 131 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 132 133 /* Define phy_reset function to boot the MC based on mcinitcmd. 134 * This happens late enough to properly fixup u-boot env MAC addresses. 135 */ 136 #define CONFIG_RESET_PHY_R 137 138 /* 139 * Carve out a DDR region which will not be used by u-boot/Linux 140 * 141 * It will be used by MC and Debug Server. The MC region must be 142 * 512MB aligned, so the min size to hide is 512MB. 143 */ 144 #ifdef CONFIG_FSL_MC_ENET 145 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) 146 #endif 147 148 /* Miscellaneous configurable options */ 149 150 /* Physical Memory Map */ 151 /* fixme: these need to be checked against the board */ 152 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 153 154 #define CONFIG_HWCONFIG 155 #define HWCONFIG_BUFFER_SIZE 128 156 157 /* Initial environment variables */ 158 #define CONFIG_EXTRA_ENV_SETTINGS \ 159 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 160 "loadaddr=0x80100000\0" \ 161 "kernel_addr=0x100000\0" \ 162 "ramdisk_addr=0x800000\0" \ 163 "ramdisk_size=0x2000000\0" \ 164 "fdt_high=0xa0000000\0" \ 165 "initrd_high=0xffffffffffffffff\0" \ 166 "kernel_start=0x581000000\0" \ 167 "kernel_load=0xa0000000\0" \ 168 "kernel_size=0x2800000\0" \ 169 "console=ttyAMA0,38400n8\0" \ 170 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 171 " 0x580e00000 \0" 172 173 #ifndef CONFIG_TFABOOT 174 #ifdef CONFIG_SD_BOOT 175 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 176 " fsl_mc apply dpl 0x80200000 &&" \ 177 " mmc read $kernel_load $kernel_start" \ 178 " $kernel_size && bootm $kernel_load" 179 #else 180 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 181 " cp.b $kernel_start $kernel_load" \ 182 " $kernel_size && bootm $kernel_load" 183 #endif 184 #endif 185 186 /* Monitor Command Prompt */ 187 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 188 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 189 190 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 191 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 192 #define CONFIG_SPL_MAX_SIZE 0x16000 193 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 194 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 195 196 #ifdef CONFIG_NAND_BOOT 197 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 198 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 199 #endif 200 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 201 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 202 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 203 204 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 205 206 #include <asm/arch/soc.h> 207 208 #endif /* __LS2_COMMON_H */ 209