1config SYS_FSL_DDR 2 bool 3 help 4 Select Freescale General DDR driver, shared between most Freescale 5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based 6 Layerscape SoCs (such as ls2080a). 7 8config SYS_FSL_MMDC 9 bool 10 help 11 Select Freescale Multi Mode DDR controller (MMDC). 12 13if SYS_FSL_DDR || SYS_FSL_MMDC 14 15config SYS_FSL_DDR_BE 16 bool 17 help 18 Access DDR registers in big-endian 19 20config SYS_FSL_DDR_LE 21 bool 22 help 23 Access DDR registers in little-endian 24 25config FSL_DDR_BIST 26 bool 27 28config FSL_DDR_INTERACTIVE 29 bool 30 31config FSL_DDR_SYNC_REFRESH 32 bool 33 34config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 35 bool 36 37menu "Freescale DDR controllers" 38 depends on SYS_FSL_DDR 39 40config SYS_NUM_DDR_CTLRS 41 int "Maximum DDR controllers" 42 default 3 if ARCH_LS2080A || \ 43 ARCH_T4240 44 default 2 if ARCH_B4860 || \ 45 ARCH_BSC9132 || \ 46 ARCH_P4080 || \ 47 ARCH_P5040 || \ 48 ARCH_LX2160A || \ 49 ARCH_LX2162A 50 default 1 51 52config SYS_FSL_DDR_VER 53 int 54 default 50 if SYS_FSL_DDR_VER_50 55 default 47 if SYS_FSL_DDR_VER_47 56 default 46 if SYS_FSL_DDR_VER_46 57 default 44 if SYS_FSL_DDR_VER_44 58 59config SYS_FSL_DDR_VER_50 60 bool 61 62config SYS_FSL_DDR_VER_47 63 bool 64 65config SYS_FSL_DDR_VER_46 66 bool 67 68config SYS_FSL_DDR_VER_44 69 bool 70 71config SYS_FSL_DDRC_GEN1 72 bool 73 help 74 Enable Freescale DDR controller. 75 76config SYS_FSL_DDRC_GEN2 77 bool 78 depends on !MPC86xx 79 help 80 Enable Freescale DDR2 controller. 81 82config SYS_FSL_DDRC_GEN3 83 bool 84 depends on PPC 85 help 86 Enable Freescale DDR3 controller for PowerPC SoCs. 87 88config SYS_FSL_DDRC_ARM_GEN3 89 bool 90 depends on ARM 91 help 92 Enable Freescale DDR3 controller for ARM SoCs. 93 94config SYS_FSL_DDRC_GEN4 95 bool 96 help 97 Enable Freescale DDR4 controller. 98 99config SYS_FSL_HAS_DDR4 100 bool 101 102config SYS_FSL_HAS_DDR3 103 bool 104 105config SYS_FSL_HAS_DDR2 106 bool 107 108config SYS_FSL_HAS_DDR1 109 bool 110 111choice 112 prompt "DDR technology" 113 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4 114 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3 115 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2 116 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1 117 118config SYS_FSL_DDR4 119 bool "Freescale DDR4 controller" 120 depends on SYS_FSL_HAS_DDR4 121 imply DDR_SPD 122 select SYS_FSL_DDRC_GEN4 123 124config SYS_FSL_DDR3 125 bool "Freescale DDR3 controller" 126 depends on SYS_FSL_HAS_DDR3 127 imply DDR_SPD 128 select SYS_FSL_DDRC_GEN3 if PPC 129 select SYS_FSL_DDRC_ARM_GEN3 if ARM 130 131config SYS_FSL_DDR2 132 bool "Freescale DDR2 controller" 133 depends on SYS_FSL_HAS_DDR2 134 imply DDR_SPD 135 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) 136 137config SYS_FSL_DDR1 138 bool "Freescale DDR1 controller" 139 depends on SYS_FSL_HAS_DDR1 140 imply DDR_SPD 141 select SYS_FSL_DDRC_GEN1 142 143endchoice 144 145endmenu 146 147config FSL_DMA 148 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER 149 150config DDR_ECC 151 bool "ECC DDR memory support" 152 153config DDR_ECC_CMD 154 bool "Access the ECC features of the memory controller" 155 depends on DDR_ECC && MPC83xx 156 default y 157 158config ECC_INIT_VIA_DDRCONTROLLER 159 bool "DDR Memory controller initializes memory." 160 help 161 Use the DDR controller to auto initialize memory. If not enabled, 162 the DMA controller is responsible for doing this. 163 164endif 165 166config SYS_FSL_ERRATUM_A008378 167 bool 168 169config SYS_FSL_ERRATUM_A008109 170 bool 171 172config SYS_FSL_ERRATUM_A008511 173 bool 174 175config SYS_FSL_ERRATUM_A009663 176 bool 177 178config SYS_FSL_ERRATUM_A009801 179 bool 180 181config SYS_FSL_ERRATUM_A009803 182 bool 183 184config SYS_FSL_ERRATUM_A009942 185 bool 186 187config SYS_FSL_ERRATUM_A010165 188 bool 189 190config SYS_FSL_ERRATUM_NMG_DDR120 191 bool 192 193config SYS_FSL_ERRATUM_DDR_115 194 bool 195 196config SYS_FSL_ERRATUM_DDR111_DDR134 197 bool 198 199config SYS_FSL_ERRATUM_DDR_A003 200 bool 201 202config SYS_FSL_ERRATUM_DDR_A003474 203 bool 204