1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007-2013 Tensilica, Inc. 4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <asm/arch/core.h> 11 #include <asm/addrspace.h> 12 #include <asm/config.h> 13 14 /* 15 * The 'xtfpga' board describes a set of very similar boards with only minimal 16 * differences. 17 */ 18 19 /*=====================*/ 20 /* Board and Processor */ 21 /*=====================*/ 22 23 #define CONFIG_XTFPGA 24 25 /* FPGA CPU freq after init */ 26 #define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) 27 28 /*===================*/ 29 /* RAM Layout */ 30 /*===================*/ 31 32 #if XCHAL_HAVE_PTP_MMU 33 #define CONFIG_SYS_MEMORY_BASE \ 34 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) 35 #define CONFIG_SYS_IO_BASE 0xf0000000 36 #else 37 #define CONFIG_SYS_MEMORY_BASE 0x60000000 38 #define CONFIG_SYS_IO_BASE 0x90000000 39 #define CONFIG_MAX_MEM_MAPPED 0x10000000 40 #endif 41 42 /* Onboard RAM sizes: 43 * 44 * LX60 0x04000000 64 MB 45 * LX110 0x03000000 48 MB 46 * LX200 0x06000000 96 MB 47 * ML605 0x18000000 384 MB 48 * KC705 0x38000000 896 MB 49 * 50 * noMMU configurations can only see first 256MB of onboard memory. 51 */ 52 53 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 54 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE 55 #else 56 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 57 #endif 58 59 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) 60 61 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ 62 #ifdef CONFIG_XTFPGA_LX60 63 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ 64 #else 65 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ 66 #endif 67 68 /* Linux boot param area in RAM (used only when booting linux) */ 69 #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) 70 71 /* Memory test is destructive so default must not overlap vectors or U-Boot*/ 72 73 /* Load address for stand-alone applications. 74 * MEMADDR cannot be used here, because the definition needs to be 75 * a plain number as it's used as -Ttext argument for ld in standalone 76 * example makefile. 77 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. 78 */ 79 #if XCHAL_HAVE_PTP_MMU 80 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR 81 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 82 #else 83 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 84 #endif 85 #else 86 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 87 #endif 88 89 #if defined(CONFIG_MAX_MEM_MAPPED) && \ 90 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE 91 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED 92 #else 93 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE 94 #endif 95 96 #define XTENSA_SYS_TEXT_ADDR \ 97 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) 98 99 /*==============================*/ 100 /* U-Boot general configuration */ 101 /*==============================*/ 102 103 #define CONFIG_BOARD_POSTCLK_INIT 104 105 #define CONFIG_BOOTFILE "uImage" 106 /* Console I/O Buffer Size */ 107 #define CONFIG_SYS_CBSIZE 1024 108 /* Boot Argument Buffer Size */ 109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 110 111 /*==============================*/ 112 /* U-Boot autoboot configuration */ 113 /*==============================*/ 114 115 116 /*=========================================*/ 117 /* FPGA Registers (board info and control) */ 118 /*=========================================*/ 119 120 /* 121 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier 122 * releases may not provide any/all of these registers or at these offsets. 123 * Some of the FPGA registers are broken down into bitfields described by 124 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. 125 */ 126 127 /* Date of FPGA bitstream build in binary coded decimal (BCD) */ 128 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) 129 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ 130 #define FPGAREG_MTH_WIDTH 8 131 #define FPGAREG_MTH_MASK 0xFF000000 132 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ 133 #define FPGAREG_DAY_WIDTH 8 134 #define FPGAREG_DAY_MASK 0x00FF0000 135 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ 136 #define FPGAREG_YEAR_WIDTH 16 137 #define FPGAREG_YEAR_MASK 0x0000FFFF 138 139 /* FPGA core clock frequency in Hz (also input to UART) */ 140 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ 141 142 /* 143 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): 144 * Bits 0..5 set the lower 6 bits of the default ethernet MAC. 145 * Bit 6 is reserved for future use by Tensilica. 146 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to 147 * the base of flash * (when on/1) or to the base of RAM (when off/0). 148 */ 149 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) 150 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ 151 #define FPGAREG_MAC_WIDTH 6 152 #define FPGAREG_MAC_MASK 0x3f 153 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ 154 #define FPGAREG_BOOT_WIDTH 1 155 #define FPGAREG_BOOT_MASK 0x80 156 #define FPGAREG_BOOT_RAM 0 157 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) 158 159 /* Force hard reset of board by writing a code to this register */ 160 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ 161 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ 162 163 /*====================*/ 164 /* Serial Driver Info */ 165 /*====================*/ 166 167 #define CONFIG_SYS_NS16550_SERIAL 168 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 169 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ 170 171 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ 172 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ 173 174 /*======================*/ 175 /* Ethernet Driver Info */ 176 /*======================*/ 177 178 #define CONFIG_ETHBASE 00:50:C2:13:6f:00 179 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) 180 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) 181 182 /*=====================*/ 183 /* Flash & Environment */ 184 /*=====================*/ 185 186 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 188 #ifdef CONFIG_XTFPGA_LX60 189 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ 190 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ 191 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ 192 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 193 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 194 #elif defined(CONFIG_XTFPGA_KC705) 195 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ 196 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 197 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 198 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) 199 # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) 200 #else 201 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ 202 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 203 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 204 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 205 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 206 #endif 207 #define CONFIG_SYS_MAX_FLASH_SECT \ 208 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ 209 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) 210 211 /* 212 * Put environment in top block (64kB) 213 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB 214 */ 215 216 /* print 'E' for empty sector on flinfo */ 217 #define CONFIG_SYS_FLASH_EMPTY_INFO 218 219 #endif /* __CONFIG_H */ 220