1 2menuconfig MTD_RAW_NAND 3 bool "Raw NAND Device Support" 4if MTD_RAW_NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SYS_NAND_DRIVER_ECC_LAYOUT 13 bool 14 help 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 17 18config SYS_NAND_USE_FLASH_BBT 19 bool "Enable BBT (Bad Block Table) support" 20 help 21 Enable the BBT (Bad Block Table) usage. 22 23config NAND_ATMEL 24 bool "Support Atmel NAND controller" 25 imply SYS_NAND_USE_FLASH_BBT 26 help 27 Enable this driver for NAND flash platforms using an Atmel NAND 28 controller. 29 30if NAND_ATMEL 31 32config ATMEL_NAND_HWECC 33 bool "Atmel Hardware ECC" 34 35config ATMEL_NAND_HW_PMECC 36 bool "Atmel Programmable Multibit ECC (PMECC)" 37 select ATMEL_NAND_HWECC 38 help 39 The Programmable Multibit ECC (PMECC) controller is a programmable 40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. 41 42config PMECC_CAP 43 int "PMECC Correctable ECC Bits" 44 depends on ATMEL_NAND_HW_PMECC 45 default 2 46 help 47 Correctable ECC bits, can be 2, 4, 8, 12, and 24. 48 49config PMECC_SECTOR_SIZE 50 int "PMECC Sector Size" 51 depends on ATMEL_NAND_HW_PMECC 52 default 512 53 help 54 Sector size, in bytes, can be 512 or 1024. 55 56config SPL_GENERATE_ATMEL_PMECC_HEADER 57 bool "Atmel PMECC Header Generation" 58 select ATMEL_NAND_HWECC 59 select ATMEL_NAND_HW_PMECC 60 help 61 Generate Programmable Multibit ECC (PMECC) header for SPL image. 62 63endif 64 65config NAND_BRCMNAND 66 bool "Support Broadcom NAND controller" 67 depends on OF_CONTROL && DM && DM_MTD 68 help 69 Enable the driver for NAND flash on platforms using a Broadcom NAND 70 controller. 71 72config NAND_BRCMNAND_6368 73 bool "Support Broadcom NAND controller on bcm6368" 74 depends on NAND_BRCMNAND && ARCH_BMIPS 75 help 76 Enable support for broadcom nand driver on bcm6368. 77 78config NAND_BRCMNAND_68360 79 bool "Support Broadcom NAND controller on bcm68360" 80 depends on NAND_BRCMNAND && ARCH_BCM68360 81 help 82 Enable support for broadcom nand driver on bcm68360. 83 84config NAND_BRCMNAND_6838 85 bool "Support Broadcom NAND controller on bcm6838" 86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 87 help 88 Enable support for broadcom nand driver on bcm6838. 89 90config NAND_BRCMNAND_6858 91 bool "Support Broadcom NAND controller on bcm6858" 92 depends on NAND_BRCMNAND && ARCH_BCM6858 93 help 94 Enable support for broadcom nand driver on bcm6858. 95 96config NAND_BRCMNAND_63158 97 bool "Support Broadcom NAND controller on bcm63158" 98 depends on NAND_BRCMNAND && ARCH_BCM63158 99 help 100 Enable support for broadcom nand driver on bcm63158. 101 102config NAND_DAVINCI 103 bool "Support TI Davinci NAND controller" 104 help 105 Enable this driver for NAND flash controllers available in TI Davinci 106 and Keystone2 platforms 107 108config KEYSTONE_RBL_NAND 109 depends on ARCH_KEYSTONE 110 def_bool y 111 112config SPL_NAND_LOAD 113 def_bool y 114 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT 115 116config NAND_DENALI 117 bool 118 select SYS_NAND_SELF_INIT 119 imply CMD_NAND 120 121config NAND_DENALI_DT 122 bool "Support Denali NAND controller as a DT device" 123 select NAND_DENALI 124 depends on OF_CONTROL && DM_MTD 125 help 126 Enable the driver for NAND flash on platforms using a Denali NAND 127 controller as a DT device. 128 129config NAND_FSL_ELBC 130 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver" 131 depends on FSL_ELBC 132 help 133 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver. 134 135config NAND_FSL_IFC 136 bool "Support Freescale Integrated Flash Controller NAND driver" 137 help 138 Enable the Freescale Integrated Flash Controller NAND driver. 139 140config NAND_LPC32XX_MLC 141 bool "Support LPC32XX_MLC controller" 142 help 143 Enable the LPC32XX MLC NAND controller. 144 145config NAND_LPC32XX_SLC 146 bool "Support LPC32XX_SLC controller" 147 help 148 Enable the LPC32XX SLC NAND controller. 149 150config NAND_OMAP_GPMC 151 bool "Support OMAP GPMC NAND controller" 152 depends on ARCH_OMAP2PLUS 153 help 154 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 155 GPMC controller is used for parallel NAND flash devices, and can 156 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 157 and BCH16 ECC algorithms. 158 159if NAND_OMAP_GPMC 160 161config NAND_OMAP_GPMC_PREFETCH 162 bool "Enable GPMC Prefetch" 163 default y 164 help 165 On OMAP platforms that use the GPMC controller 166 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 167 uses the prefetch mode to speed up read operations. 168 169config NAND_OMAP_ELM 170 bool "Enable ELM driver for OMAPxx and AMxx platforms." 171 depends on !OMAP34XX 172 help 173 ELM controller is used for ECC error detection (not ECC calculation) 174 of BCH4, BCH8 and BCH16 ECC algorithms. 175 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 176 thus such SoC platforms need to depend on software library for ECC error 177 detection. However ECC calculation on such plaforms would still be 178 done by GPMC controller. 179 180choice 181 prompt "ECC scheme" 182 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 183 help 184 On OMAP platforms, this CONFIG specifies NAND ECC scheme. 185 It can take following values: 186 OMAP_ECC_HAM1_CODE_SW 187 1-bit Hamming code using software lib. 188 (for legacy devices only) 189 OMAP_ECC_HAM1_CODE_HW 190 1-bit Hamming code using GPMC hardware. 191 (for legacy devices only) 192 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW 193 4-bit BCH code (unsupported) 194 OMAP_ECC_BCH4_CODE_HW 195 4-bit BCH code (unsupported) 196 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 197 8-bit BCH code with 198 - ecc calculation using GPMC hardware engine, 199 - error detection using software library. 200 - requires CONFIG_BCH to enable software BCH library 201 (For legacy device which do not have ELM h/w engine) 202 OMAP_ECC_BCH8_CODE_HW 203 8-bit BCH code with 204 - ecc calculation using GPMC hardware engine, 205 - error detection using ELM hardware engine. 206 OMAP_ECC_BCH16_CODE_HW 207 16-bit BCH code with 208 - ecc calculation using GPMC hardware engine, 209 - error detection using ELM hardware engine. 210 211 How to select ECC scheme on OMAP and AMxx platforms ? 212 ----------------------------------------------------- 213 Though higher ECC schemes have more capability to detect and correct 214 bit-flips, but still selection of ECC scheme is dependent on following 215 - hardware engines present in SoC. 216 Some legacy OMAP SoC do not have ELM h/w engine thus such 217 SoC cannot support BCHx_HW ECC schemes. 218 - size of OOB/Spare region 219 With higher ECC schemes, more OOB/Spare area is required to 220 store ECC. So choice of ECC scheme is limited by NAND oobsize. 221 222 In general following expression can help: 223 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES 224 where 225 NAND_OOBSIZE = number of bytes available in 226 OOB/spare area per NAND page. 227 NAND_PAGESIZE = bytes in main-area of NAND page. 228 ECC_BYTES = number of ECC bytes generated to 229 protect 512 bytes of data, which is: 230 3 for HAM1_xx ecc schemes 231 7 for BCH4_xx ecc schemes 232 14 for BCH8_xx ecc schemes 233 26 for BCH16_xx ecc schemes 234 235 example to check for BCH16 on 2K page NAND 236 NAND_PAGESIZE = 2048 237 NAND_OOBSIZE = 64 238 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE 239 Thus BCH16 cannot be supported on 2K page NAND. 240 241 However, for 4K pagesize NAND 242 NAND_PAGESIZE = 4096 243 NAND_OOBSIZE = 224 244 ECC_BYTES = 26 245 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE 246 Thus BCH16 can be supported on 4K page NAND. 247 248config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW 249 bool "1-bit Hamming code using software lib" 250 251config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW 252 bool "1-bit Hamming code using GPMC hardware" 253 254config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW 255 bool "8-bit BCH code with HW calculation SW error detection" 256 257config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 258 bool "8-bit BCH code with HW calculation and error detection" 259 260config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW 261 bool "16-bit BCH code with HW calculation and error detection" 262 263endchoice 264 265config NAND_OMAP_ECCSCHEME 266 int 267 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW 268 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW 269 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW 270 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW 271 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW 272 help 273 This must be kept in sync with the enum in 274 include/linux/mtd/omap_gpmc.h 275 276endif 277 278config NAND_VF610_NFC 279 bool "Support for Freescale NFC for VF610" 280 select SYS_NAND_SELF_INIT 281 select SYS_NAND_DRIVER_ECC_LAYOUT 282 imply CMD_NAND 283 help 284 Enables support for NAND Flash Controller on some Freescale 285 processors like the VF610, MCF54418 or Kinetis K70. 286 The driver supports a maximum 2k page size. The driver 287 currently does not support hardware ECC. 288 289if NAND_VF610_NFC 290 291config NAND_VF610_NFC_DT 292 bool "Support Vybrid's vf610 NAND controller as a DT device" 293 depends on OF_CONTROL && DM_MTD 294 help 295 Enable the driver for Vybrid's vf610 NAND flash on platforms 296 using device tree. 297 298choice 299 prompt "Hardware ECC strength" 300 depends on NAND_VF610_NFC 301 default SYS_NAND_VF610_NFC_45_ECC_BYTES 302 help 303 Select the ECC strength used in the hardware BCH ECC block. 304 305config SYS_NAND_VF610_NFC_45_ECC_BYTES 306 bool "24-error correction (45 ECC bytes)" 307 308config SYS_NAND_VF610_NFC_60_ECC_BYTES 309 bool "32-error correction (60 ECC bytes)" 310 311endchoice 312 313endif 314 315config NAND_PXA3XX 316 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 317 select SYS_NAND_SELF_INIT 318 select DM_MTD 319 select REGMAP 320 select SYSCON 321 imply CMD_NAND 322 help 323 This enables the driver for the NAND flash device found on 324 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 325 326config NAND_SUNXI 327 bool "Support for NAND on Allwinner SoCs" 328 default ARCH_SUNXI 329 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 330 select SYS_NAND_SELF_INIT 331 select SYS_NAND_U_BOOT_LOCATIONS 332 select SPL_NAND_SUPPORT 333 imply CMD_NAND 334 ---help--- 335 Enable support for NAND. This option enables the standard and 336 SPL drivers. 337 The SPL driver only supports reading from the NAND using DMA 338 transfers. 339 340if NAND_SUNXI 341 342config NAND_SUNXI_SPL_ECC_STRENGTH 343 int "Allwinner NAND SPL ECC Strength" 344 default 64 345 346config NAND_SUNXI_SPL_ECC_SIZE 347 int "Allwinner NAND SPL ECC Step Size" 348 default 1024 349 350config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 351 int "Allwinner NAND SPL Usable Page Size" 352 default 1024 353 354endif 355 356config NAND_ARASAN 357 bool "Configure Arasan Nand" 358 select SYS_NAND_SELF_INIT 359 depends on DM_MTD 360 imply CMD_NAND 361 help 362 This enables Nand driver support for Arasan nand flash 363 controller. This uses the hardware ECC for read and 364 write operations. 365 366config NAND_MXC 367 bool "MXC NAND support" 368 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 369 imply CMD_NAND 370 help 371 This enables the NAND driver for the NAND flash controller on the 372 i.MX27 / i.MX31 / i.MX5 processors. 373 374config NAND_MXS 375 bool "MXS NAND support" 376 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M 377 select SYS_NAND_SELF_INIT 378 imply CMD_NAND 379 select APBH_DMA 380 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 381 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 382 help 383 This enables NAND driver for the NAND flash controller on the 384 MXS processors. 385 386if NAND_MXS 387 388config NAND_MXS_DT 389 bool "Support MXS NAND controller as a DT device" 390 depends on OF_CONTROL && DM_MTD 391 help 392 Enable the driver for MXS NAND flash on platforms using 393 device tree. 394 395config NAND_MXS_USE_MINIMUM_ECC 396 bool "Use minimum ECC strength supported by the controller" 397 default false 398 399endif 400 401config NAND_MXIC 402 bool "Macronix raw NAND controller" 403 select SYS_NAND_SELF_INIT 404 help 405 This selects the Macronix raw NAND controller driver. 406 407config NAND_ZYNQ 408 bool "Support for Zynq Nand controller" 409 select SYS_NAND_SELF_INIT 410 select DM_MTD 411 imply CMD_NAND 412 help 413 This enables Nand driver support for Nand flash controller 414 found on Zynq SoC. 415 416config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 417 bool "Enable use of 1st stage bootloader timing for NAND" 418 depends on NAND_ZYNQ 419 help 420 This flag prevent U-boot reconfigure NAND flash controller and reuse 421 the NAND timing from 1st stage bootloader. 422 423config NAND_OCTEONTX 424 bool "Support for OcteonTX NAND controller" 425 select SYS_NAND_SELF_INIT 426 imply CMD_NAND 427 help 428 This enables Nand flash controller hardware found on the OcteonTX 429 processors. 430 431config NAND_OCTEONTX_HW_ECC 432 bool "Support Hardware ECC for OcteonTX NAND controller" 433 depends on NAND_OCTEONTX 434 default y 435 help 436 This enables Hardware BCH engine found on the OcteonTX processors to 437 support ECC for NAND flash controller. 438 439config NAND_STM32_FMC2 440 bool "Support for NAND controller on STM32MP SoCs" 441 depends on ARCH_STM32MP 442 select SYS_NAND_SELF_INIT 443 imply CMD_NAND 444 help 445 Enables support for NAND Flash chips on SoCs containing the FMC2 446 NAND controller. This controller is found on STM32MP SoCs. 447 The controller supports a maximum 8k page size and supports 448 a maximum 8-bit correction error per sector of 512 bytes. 449 450config CORTINA_NAND 451 bool "Support for NAND controller on Cortina-Access SoCs" 452 depends on CORTINA_PLATFORM 453 select SYS_NAND_SELF_INIT 454 select DM_MTD 455 imply CMD_NAND 456 help 457 Enables support for NAND Flash chips on Coartina-Access SoCs platform 458 This controller is found on Presidio/Venus SoCs. 459 The controller supports a maximum 8k page size and supports 460 a maximum 40-bit error correction per sector of 1024 bytes. 461 462config ROCKCHIP_NAND 463 bool "Support for NAND controller on Rockchip SoCs" 464 depends on ARCH_ROCKCHIP 465 select SYS_NAND_SELF_INIT 466 select DM_MTD 467 imply CMD_NAND 468 help 469 Enables support for NAND Flash chips on Rockchip SoCs platform. 470 This controller is found on Rockchip SoCs. 471 There are four different versions of NAND FLASH Controllers, 472 including: 473 NFC v600: RK2928, RK3066, RK3188 474 NFC v622: RK3036, RK3128 475 NFC v800: RK3308, RV1108 476 NFC v900: PX30, RK3326 477 478comment "Generic NAND options" 479 480config SYS_NAND_BLOCK_SIZE 481 hex "NAND chip eraseblock size" 482 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT 483 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC 484 help 485 Number of data bytes in one eraseblock for the NAND chip on the 486 board. This is the multiple of NAND_PAGE_SIZE and the number of 487 pages. 488 489config SYS_NAND_ONFI_DETECTION 490 bool "Enable detection of ONFI compliant devices during probe" 491 help 492 Enables detection of ONFI compliant devices during probe. 493 And fetching device parameters flashed on device, by parsing 494 ONFI parameter page. 495 496config SYS_NAND_PAGE_COUNT 497 hex "NAND chip page count" 498 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ 499 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE) 500 help 501 Number of pages in the NAND chip. 502 503config SYS_NAND_PAGE_SIZE 504 hex "NAND chip page size" 505 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ 506 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ 507 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER 508 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC 509 help 510 Number of data bytes in one page for the NAND chip on the 511 board, not including the OOB area. 512 513config SYS_NAND_OOBSIZE 514 hex "NAND chip OOB size" 515 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ 516 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ 517 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER 518 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC 519 help 520 Number of bytes in the Out-Of-Band area for the NAND chip on 521 the board. 522 523# Enhance depends when converting drivers to Kconfig which use this config 524# option (mxc_nand, ndfc, omap_gpmc). 525config SYS_NAND_BUSWIDTH_16BIT 526 bool "Use 16-bit NAND interface" 527 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 528 help 529 Indicates that NAND device has 16-bit wide data-bus. In absence of this 530 config, bus-width of NAND device is assumed to be either 8-bit and later 531 determined by reading ONFI params. 532 Above config is useful when NAND device's bus-width information cannot 533 be determined from on-chip ONFI params, like in following scenarios: 534 - SPL boot does not support reading of ONFI parameters. This is done to 535 keep SPL code foot-print small. 536 - In current U-Boot flow using nand_init(), driver initialization 537 happens in board_nand_init() which is called before any device probe 538 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 539 not available while configuring controller. So a static CONFIG_NAND_xx 540 is needed to know the device's bus-width in advance. 541 542if SPL 543 544config SYS_NAND_5_ADDR_CYCLE 545 bool "Wait 5 address cycles during NAND commands" 546 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \ 547 (SPL_NAND_SUPPORT && NAND_ATMEL) 548 default y 549 help 550 Some controllers require waiting for 5 address cycles when issuing 551 some commands, on NAND chips larger than 128MiB. 552 553choice 554 prompt "NAND bad block marker/indicator position in the OOB" 555 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \ 556 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC) 557 default HAS_NAND_LARGE_BADBLOCK_POS 558 help 559 In the OOB, which position contains the badblock information. 560 561config HAS_NAND_LARGE_BADBLOCK_POS 562 bool "Set the bad block marker/indicator to the 'large' position" 563 564config HAS_NAND_SMALL_BADBLOCK_POS 565 bool "Set the bad block marker/indicator to the 'small' position" 566 567endchoice 568 569config SYS_NAND_BAD_BLOCK_POS 570 int 571 default 0 if HAS_NAND_LARGE_BADBLOCK_POS 572 default 5 if HAS_NAND_SMALL_BADBLOCK_POS 573 574config SYS_NAND_U_BOOT_LOCATIONS 575 bool "Define U-boot binaries locations in NAND" 576 help 577 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 578 This option should not be enabled when compiling U-boot for boards 579 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 580 file. 581 582config SYS_NAND_U_BOOT_OFFS 583 hex "Location in NAND to read U-Boot from" 584 default 0x800000 if NAND_SUNXI 585 depends on SYS_NAND_U_BOOT_LOCATIONS 586 help 587 Set the offset from the start of the nand where u-boot should be 588 loaded from. 589 590config SYS_NAND_U_BOOT_OFFS_REDUND 591 hex "Location in NAND to read U-Boot from" 592 default SYS_NAND_U_BOOT_OFFS 593 depends on SYS_NAND_U_BOOT_LOCATIONS 594 help 595 Set the offset from the start of the nand where the redundant u-boot 596 should be loaded from. 597 598config SPL_NAND_AM33XX_BCH 599 bool "Enables SPL-NAND driver which supports ELM based" 600 depends on NAND_OMAP_GPMC && !OMAP34XX 601 default y 602 help 603 Hardware ECC correction. This is useful for platforms which have ELM 604 hardware engine and use NAND boot mode. 605 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 606 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 607 SPL-NAND driver with software ECC correction support. 608 609config SPL_NAND_DENALI 610 bool "Support Denali NAND controller for SPL" 611 help 612 This is a small implementation of the Denali NAND controller 613 for use on SPL. 614 615config NAND_DENALI_SPARE_AREA_SKIP_BYTES 616 int "Number of bytes skipped in OOB area" 617 depends on SPL_NAND_DENALI 618 range 0 63 619 help 620 This option specifies the number of bytes to skip from the beginning 621 of OOB area before last ECC sector data starts. This is potentially 622 used to preserve the bad block marker in the OOB area. 623 624config SPL_NAND_SIMPLE 625 bool "Use simple SPL NAND driver" 626 depends on !SPL_NAND_AM33XX_BCH 627 help 628 Support for NAND boot using simple NAND drivers that 629 expose the cmd_ctrl() interface. 630endif 631 632endif # if NAND 633