1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_MALTA 16 bool "Support malta" 17 select BOARD_EARLY_INIT_R 18 select DM 19 select DM_SERIAL 20 select PCI 21 select DM_ETH 22 select DYNAMIC_IO_PORT_BASE 23 select MIPS_CM 24 select MIPS_INSERT_BOOT_CONFIG 25 select SYS_CACHE_SHIFT_6 26 select MIPS_L2_CACHE 27 select OF_CONTROL 28 select OF_ISA_BUS 29 select PCI_MAP_SYSTEM_MEMORY 30 select ROM_EXCEPTION_VECTORS 31 select SUPPORTS_BIG_ENDIAN 32 select SUPPORTS_CPU_MIPS32_R1 33 select SUPPORTS_CPU_MIPS32_R2 34 select SUPPORTS_CPU_MIPS32_R6 35 select SUPPORTS_CPU_MIPS64_R1 36 select SUPPORTS_CPU_MIPS64_R2 37 select SUPPORTS_CPU_MIPS64_R6 38 select SUPPORTS_LITTLE_ENDIAN 39 select SWAP_IO_SPACE 40 imply CMD_DM 41 42config TARGET_VCT 43 bool "Support vct" 44 select ROM_EXCEPTION_VECTORS 45 select SUPPORTS_BIG_ENDIAN 46 select SUPPORTS_CPU_MIPS32_R1 47 select SUPPORTS_CPU_MIPS32_R2 48 select SYS_MIPS_CACHE_INIT_RAM_LOAD 49 50config ARCH_ATH79 51 bool "Support QCA/Atheros ath79" 52 select DM 53 select OF_CONTROL 54 imply CMD_DM 55 56config ARCH_MSCC 57 bool "Support MSCC VCore-III" 58 select OF_CONTROL 59 select DM 60 61config ARCH_BMIPS 62 bool "Support BMIPS SoCs" 63 select CLK 64 select CPU 65 select DM 66 select OF_CONTROL 67 select RAM 68 select SYSRESET 69 imply CMD_DM 70 71config ARCH_MTMIPS 72 bool "Support MediaTek MIPS platforms" 73 select CLK 74 imply CMD_DM 75 select DISPLAY_CPUINFO 76 select DM 77 imply DM_ETH 78 imply DM_GPIO 79 select DM_RESET 80 select DM_SERIAL 81 select PINCTRL 82 select PINMUX 83 select PINCONF 84 select RESET_MTMIPS 85 imply DM_SPI 86 imply DM_SPI_FLASH 87 select LAST_STAGE_INIT 88 select MIPS_TUNE_24KC 89 select OF_CONTROL 90 select ROM_EXCEPTION_VECTORS 91 select SUPPORTS_CPU_MIPS32_R1 92 select SUPPORTS_CPU_MIPS32_R2 93 select SUPPORTS_LITTLE_ENDIAN 94 select SUPPORT_SPL 95 96config ARCH_JZ47XX 97 bool "Support Ingenic JZ47xx" 98 select SUPPORT_SPL 99 select OF_CONTROL 100 select DM 101 102config ARCH_OCTEON 103 bool "Support Marvell Octeon CN7xxx platforms" 104 select CPU_CAVIUM_OCTEON 105 select DISPLAY_CPUINFO 106 select DMA_ADDR_T_64BIT 107 select DM 108 select DM_ETH 109 select DM_GPIO 110 select DM_I2C 111 select DM_SERIAL 112 select DM_SPI 113 select MIPS_L2_CACHE 114 select MIPS_MACH_EARLY_INIT 115 select MIPS_TUNE_OCTEON3 116 select ROM_EXCEPTION_VECTORS 117 select SUPPORTS_BIG_ENDIAN 118 select SUPPORTS_CPU_MIPS64_OCTEON 119 select PHYS_64BIT 120 select OF_CONTROL 121 select OF_LIVE 122 imply CMD_DM 123 124config MACH_PIC32 125 bool "Support Microchip PIC32" 126 select DM 127 select OF_CONTROL 128 imply CMD_DM 129 130config TARGET_BOSTON 131 bool "Support Boston" 132 select DM 133 select DM_SERIAL 134 select MIPS_CM 135 select SYS_CACHE_SHIFT_6 136 select MIPS_L2_CACHE 137 select OF_BOARD_SETUP 138 select OF_CONTROL 139 select ROM_EXCEPTION_VECTORS 140 select SUPPORTS_BIG_ENDIAN 141 select SUPPORTS_CPU_MIPS32_R1 142 select SUPPORTS_CPU_MIPS32_R2 143 select SUPPORTS_CPU_MIPS32_R6 144 select SUPPORTS_CPU_MIPS64_R1 145 select SUPPORTS_CPU_MIPS64_R2 146 select SUPPORTS_CPU_MIPS64_R6 147 select SUPPORTS_LITTLE_ENDIAN 148 imply CMD_DM 149 150config TARGET_XILFPGA 151 bool "Support Imagination Xilfpga" 152 select DM 153 select DM_ETH 154 select DM_GPIO 155 select DM_SERIAL 156 select SYS_CACHE_SHIFT_4 157 select OF_CONTROL 158 select ROM_EXCEPTION_VECTORS 159 select SUPPORTS_CPU_MIPS32_R1 160 select SUPPORTS_CPU_MIPS32_R2 161 select SUPPORTS_LITTLE_ENDIAN 162 imply CMD_DM 163 help 164 This supports IMGTEC MIPSfpga platform 165 166endchoice 167 168source "board/imgtec/boston/Kconfig" 169source "board/imgtec/malta/Kconfig" 170source "board/imgtec/xilfpga/Kconfig" 171source "arch/mips/mach-ath79/Kconfig" 172source "arch/mips/mach-mscc/Kconfig" 173source "arch/mips/mach-bmips/Kconfig" 174source "arch/mips/mach-jz47xx/Kconfig" 175source "arch/mips/mach-pic32/Kconfig" 176source "arch/mips/mach-mtmips/Kconfig" 177source "arch/mips/mach-octeon/Kconfig" 178 179if MIPS 180 181choice 182 prompt "Endianness selection" 183 help 184 Some MIPS boards can be configured for either little or big endian 185 byte order. These modes require different U-Boot images. In general there 186 is one preferred byteorder for a particular system but some systems are 187 just as commonly used in the one or the other endianness. 188 189config SYS_BIG_ENDIAN 190 bool "Big endian" 191 depends on SUPPORTS_BIG_ENDIAN 192 193config SYS_LITTLE_ENDIAN 194 bool "Little endian" 195 depends on SUPPORTS_LITTLE_ENDIAN 196 197endchoice 198 199choice 200 prompt "CPU selection" 201 default CPU_MIPS32_R2 202 203config CPU_MIPS32_R1 204 bool "MIPS32 Release 1" 205 depends on SUPPORTS_CPU_MIPS32_R1 206 select 32BIT 207 help 208 Choose this option to build an U-Boot for release 1 through 5 of the 209 MIPS32 architecture. 210 211config CPU_MIPS32_R2 212 bool "MIPS32 Release 2" 213 depends on SUPPORTS_CPU_MIPS32_R2 214 select 32BIT 215 help 216 Choose this option to build an U-Boot for release 2 through 5 of the 217 MIPS32 architecture. 218 219config CPU_MIPS32_R6 220 bool "MIPS32 Release 6" 221 depends on SUPPORTS_CPU_MIPS32_R6 222 select 32BIT 223 help 224 Choose this option to build an U-Boot for release 6 or later of the 225 MIPS32 architecture. 226 227config CPU_MIPS64_R1 228 bool "MIPS64 Release 1" 229 depends on SUPPORTS_CPU_MIPS64_R1 230 select 64BIT 231 help 232 Choose this option to build a kernel for release 1 through 5 of the 233 MIPS64 architecture. 234 235config CPU_MIPS64_R2 236 bool "MIPS64 Release 2" 237 depends on SUPPORTS_CPU_MIPS64_R2 238 select 64BIT 239 help 240 Choose this option to build a kernel for release 2 through 5 of the 241 MIPS64 architecture. 242 243config CPU_MIPS64_R6 244 bool "MIPS64 Release 6" 245 depends on SUPPORTS_CPU_MIPS64_R6 246 select 64BIT 247 help 248 Choose this option to build a kernel for release 6 or later of the 249 MIPS64 architecture. 250 251config CPU_MIPS64_OCTEON 252 bool "Marvell Octeon series of CPUs" 253 depends on SUPPORTS_CPU_MIPS64_OCTEON 254 select 64BIT 255 help 256 Choose this option for Marvell Octeon CPUs. These CPUs are between 257 MIPS64 R5 and R6 with other extensions. 258 259endchoice 260 261menu "General setup" 262 263config ROM_EXCEPTION_VECTORS 264 bool "Build U-Boot image with exception vectors" 265 help 266 Enable this to include exception vectors in the U-Boot image. This is 267 required if the U-Boot entry point is equal to the address of the 268 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 269 U-Boot booted from parallel NOR flash). 270 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 271 In that case the image size will be reduced by 0x500 bytes. 272 273config MIPS_CM_BASE 274 hex "MIPS CM GCR Base Address" 275 depends on MIPS_CM 276 default 0x16100000 if TARGET_BOSTON 277 default 0x1fbf8000 278 help 279 The physical base address at which to map the MIPS Coherence Manager 280 Global Configuration Registers (GCRs). This should be set such that 281 the GCRs occupy a region of the physical address space which is 282 otherwise unused, or at minimum that software doesn't need to access. 283 284config MIPS_CACHE_INDEX_BASE 285 hex "Index base address for cache initialisation" 286 default 0x80000000 if CPU_MIPS32 287 default 0xffffffff80000000 if CPU_MIPS64 288 help 289 This is the base address for a memory block, which is used for 290 initialising the cache lines. This is also the base address of a memory 291 block which is used for loading and filling cache lines when 292 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 293 Normally this is CKSEG0. If the MIPS system needs to move this block 294 to some SRAM or ScratchPad RAM, adapt this option accordingly. 295 296config MIPS_MACH_EARLY_INIT 297 bool "Enable mach specific very early init code" 298 help 299 Use this to enable the call to mips_mach_early_init() very early 300 from start.S. This function can be used e.g. to do some very early 301 CPU / SoC intitialization or image copying. Its called very early 302 and at this stage the PC might not match the linking address 303 (CONFIG_TEXT_BASE) - no absolute jump done until this call. 304 305config MIPS_CACHE_SETUP 306 bool "Allow generic start code to initialize and setup caches" 307 default n if SKIP_LOWLEVEL_INIT 308 default y 309 help 310 This allows the generic start code to invoke the generic initialization 311 of the CPU caches. Disabling this can be useful for RAM boot scenarios 312 (EJTAG, SPL payload) or for machines which don't need cache initialization 313 or which want to provide their own cache implementation. 314 315 If unsure, say yes. 316 317config MIPS_CACHE_DISABLE 318 bool "Allow generic start code to initially disable caches" 319 default n if SKIP_LOWLEVEL_INIT 320 default y 321 help 322 This allows the generic start code to initially disable the CPU caches 323 and run uncached until the caches are initialized and enabled. Disabling 324 this can be useful on machines which don't need cache initialization or 325 which want to provide their own cache implementation. 326 327 If unsure, say yes. 328 329config MIPS_RELOCATION_TABLE_SIZE 330 hex "Relocation table size" 331 range 0x100 0x10000 332 default "0x8000" 333 ---help--- 334 A table of relocation data will be appended to the U-Boot binary 335 and parsed in relocate_code() to fix up all offsets in the relocated 336 U-Boot. 337 338 This option allows the amount of space reserved for the table to be 339 adjusted in a range from 256 up to 64k. The default is 32k and should 340 be ok in most cases. Reduce this value to shrink the size of U-Boot 341 binary. 342 343 The build will fail and a valid size suggested if this is too small. 344 345 If unsure, leave at the default value. 346 347config RESTORE_EXCEPTION_VECTOR_BASE 348 bool "Restore exception vector base before booting linux kernel" 349 help 350 In U-Boot the exception vector base will be moved to top of memory, 351 to be used to display register dump when exception occurs. 352 But some old linux kernel does not honor the base set in CP0_EBASE. 353 A modified exception vector base will cause kernel crash. 354 355 This option will restore the exception vector base to its previous 356 value. 357 358 If unsure, say N. 359 360config OVERRIDE_EXCEPTION_VECTOR_BASE 361 bool "Override the exception vector base to be restored" 362 depends on RESTORE_EXCEPTION_VECTOR_BASE 363 help 364 Enable this option if you want to use a different exception vector 365 base rather than the previously saved one. 366 367config NEW_EXCEPTION_VECTOR_BASE 368 hex "New exception vector base" 369 depends on OVERRIDE_EXCEPTION_VECTOR_BASE 370 range 0x80000000 0xbffff000 371 default 0x80000000 372 help 373 The exception vector base to be restored before booting linux kernel 374 375config INIT_STACK_WITHOUT_MALLOC_F 376 bool "Do not reserve malloc space on initial stack" 377 help 378 Enable this option if you don't want to reserve malloc space on 379 initial stack. This is useful if the initial stack can't hold large 380 malloc space. Platform should set the malloc_base later when DRAM is 381 ready to use. 382 383config SPL_INIT_STACK_WITHOUT_MALLOC_F 384 bool "Do not reserve malloc space on initial stack in SPL" 385 help 386 Enable this option if you don't want to reserve malloc space on 387 initial stack. This is useful if the initial stack can't hold large 388 malloc space. Platform should set the malloc_base later when DRAM is 389 ready to use. 390 391config SPL_LOADER_SUPPORT 392 bool 393 help 394 Enable this option if you want to use SPL loaders without DM enabled. 395 396endmenu 397 398menu "OS boot interface" 399 400config MIPS_BOOT_CMDLINE_LEGACY 401 bool "Hand over legacy command line to Linux kernel" 402 default y 403 help 404 Enable this option if you want U-Boot to hand over the Yamon-style 405 command line to the kernel. All bootargs will be prepared as argc/argv 406 compatible list. The argument count (argc) is stored in register $a0. 407 The address of the argument list (argv) is stored in register $a1. 408 409config MIPS_BOOT_ENV_LEGACY 410 bool "Hand over legacy environment to Linux kernel" 411 default y 412 help 413 Enable this option if you want U-Boot to hand over the Yamon-style 414 environment to the kernel. Information like memory size, initrd 415 address and size will be prepared as zero-terminated key/value list. 416 The address of the environment is stored in register $a2. 417 418config MIPS_BOOT_FDT 419 bool "Hand over a flattened device tree to Linux kernel" 420 help 421 Enable this option if you want U-Boot to hand over a flattened 422 device tree to the kernel. According to UHI register $a0 will be set 423 to -2 and the FDT address is stored in $a1. 424 425endmenu 426 427config SUPPORTS_BIG_ENDIAN 428 bool 429 430config SUPPORTS_LITTLE_ENDIAN 431 bool 432 433config SUPPORTS_CPU_MIPS32_R1 434 bool 435 436config SUPPORTS_CPU_MIPS32_R2 437 bool 438 439config SUPPORTS_CPU_MIPS32_R6 440 bool 441 442config SUPPORTS_CPU_MIPS64_R1 443 bool 444 445config SUPPORTS_CPU_MIPS64_R2 446 bool 447 448config SUPPORTS_CPU_MIPS64_R6 449 bool 450 451config SUPPORTS_CPU_MIPS64_OCTEON 452 bool 453 454config CPU_CAVIUM_OCTEON 455 bool 456 457config CPU_MIPS32 458 bool 459 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 460 461config CPU_MIPS64 462 bool 463 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 464 default y if CPU_MIPS64_OCTEON 465 466config MIPS_TUNE_4KC 467 bool 468 469config MIPS_TUNE_14KC 470 bool 471 472config MIPS_TUNE_24KC 473 bool 474 475config MIPS_TUNE_34KC 476 bool 477 478config MIPS_TUNE_74KC 479 bool 480 481config MIPS_TUNE_OCTEON3 482 bool 483 484config 32BIT 485 bool 486 487config 64BIT 488 bool 489 490config SWAP_IO_SPACE 491 bool 492 493config SYS_MIPS_CACHE_INIT_RAM_LOAD 494 bool 495 496config MIPS_INIT_STACK_IN_SRAM 497 bool 498 help 499 Select this if the initial stack frame could be setup in SRAM. 500 Normally the initial stack frame is set up in DRAM which is often 501 only available after lowlevel_init. With this option the initial 502 stack frame and the early C environment is set up before 503 lowlevel_init. Thus lowlevel_init does not need to be implemented 504 in assembler. 505 506config MIPS_SRAM_INIT 507 bool 508 depends on MIPS_INIT_STACK_IN_SRAM 509 help 510 Select this if the SRAM for initial stack needs to be initialized 511 before it can be used. If enabled, a function mips_sram_init() will 512 be called just before setup_stack_gd. 513 514config DMA_ADDR_T_64BIT 515 bool 516 help 517 Select this to enable 64-bit DMA addressing 518 519config SYS_DCACHE_SIZE 520 int 521 default 0 522 help 523 The total size of the L1 Dcache, if known at compile time. 524 525config SYS_DCACHE_LINE_SIZE 526 int 527 default 0 528 help 529 The size of L1 Dcache lines, if known at compile time. 530 531config SYS_ICACHE_SIZE 532 int 533 default 0 534 help 535 The total size of the L1 ICache, if known at compile time. 536 537config SYS_ICACHE_LINE_SIZE 538 int 539 default 0 540 help 541 The size of L1 Icache lines, if known at compile time. 542 543config SYS_SCACHE_LINE_SIZE 544 int 545 default 0 546 help 547 The size of L2 cache lines, if known at compile time. 548 549 550config SYS_CACHE_SIZE_AUTO 551 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 552 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \ 553 SYS_SCACHE_LINE_SIZE = 0 554 help 555 Select this (or let it be auto-selected by not defining any cache 556 sizes) in order to allow U-Boot to automatically detect the sizes 557 of caches at runtime. This has a small cost in code size & runtime 558 so if you know the cache configuration for your system at compile 559 time it would be beneficial to configure it. 560 561config MIPS_L2_CACHE 562 bool 563 help 564 Select this if your system includes an L2 cache and you want U-Boot 565 to initialise & maintain it. 566 567config DYNAMIC_IO_PORT_BASE 568 bool 569 570config MIPS_CM 571 bool 572 help 573 Select this if your system contains a MIPS Coherence Manager and you 574 wish U-Boot to configure it or make use of it to retrieve system 575 information such as cache configuration. 576 577config MIPS_INSERT_BOOT_CONFIG 578 bool 579 help 580 Enable this to insert some board-specific boot configuration in 581 the U-Boot binary at offset 0x10. 582 583config MIPS_BOOT_CONFIG_WORD0 584 hex 585 depends on MIPS_INSERT_BOOT_CONFIG 586 default 0x420 if TARGET_MALTA 587 default 0x0 588 help 589 Value which is inserted as boot config word 0. 590 591config MIPS_BOOT_CONFIG_WORD1 592 hex 593 depends on MIPS_INSERT_BOOT_CONFIG 594 default 0x0 595 help 596 Value which is inserted as boot config word 1. 597 598endif 599 600endmenu 601