1
2config BITBANGMII
3	bool "Bit-banged ethernet MII management channel support"
4
5config MV88E6352_SWITCH
6	bool "Marvell 88E6352 switch support"
7
8menuconfig PHYLIB
9	bool "Ethernet PHY (physical media interface) support"
10	depends on NET
11	help
12	  Enable Ethernet PHY (physical media interface) support.
13
14if PHYLIB
15
16config PHY_ADDR_ENABLE
17	bool "Limit phy address"
18	default y if ARCH_SUNXI
19	help
20	  Select this if you want to control which phy address is used
21
22if PHY_ADDR_ENABLE
23config PHY_ADDR
24	int "PHY address"
25	default 1 if ARCH_SUNXI
26	default 0
27	help
28	  The address of PHY on MII bus. Usually in range of 0 to 31.
29endif
30
31config B53_SWITCH
32	bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
33	help
34	  Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
35	  This currently supports BCM53125 and similar models.
36
37if B53_SWITCH
38
39config B53_CPU_PORT
40	int "CPU port"
41	default 8
42
43config B53_PHY_PORTS
44	hex "Bitmask of PHY ports"
45
46endif # B53_SWITCH
47
48config MV88E61XX_SWITCH
49	bool "Marvell MV88E61xx Ethernet switch PHY support."
50
51if MV88E61XX_SWITCH
52
53config MV88E61XX_CPU_PORT
54	int "CPU Port"
55
56config MV88E61XX_PHY_PORTS
57	hex "Bitmask of PHY Ports"
58
59config MV88E61XX_FIXED_PORTS
60	hex "Bitmask of PHYless serdes Ports"
61
62endif # MV88E61XX_SWITCH
63
64config PHYLIB_10G
65	bool "Generic 10G PHY support"
66
67menuconfig PHY_AQUANTIA
68	bool "Aquantia Ethernet PHYs support"
69	select PHY_GIGE
70	select PHYLIB_10G
71
72config PHY_AQUANTIA_UPLOAD_FW
73	bool "Aquantia firmware loading support"
74	depends on PHY_AQUANTIA
75	help
76		Aquantia PHYs use firmware which can be either loaded automatically
77		from storage directly attached to the phy or loaded by the boot loader
78		via MDIO commands.  The firmware is loaded from a file, specified by
79		the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
80
81config PHY_AQUANTIA_FW_PART
82	string "Aquantia firmware partition"
83	depends on PHY_AQUANTIA_UPLOAD_FW
84	help
85		Partition containing the firmware file.
86
87config PHY_AQUANTIA_FW_NAME
88	string "Aquantia firmware filename"
89	depends on PHY_AQUANTIA_UPLOAD_FW
90	help
91		Firmware filename.
92
93config PHY_ATHEROS
94	bool "Atheros Ethernet PHYs support"
95
96config PHY_BROADCOM
97	bool "Broadcom Ethernet PHYs support"
98
99config PHY_CORTINA
100	bool "Cortina Ethernet PHYs support"
101
102config SYS_CORTINA_NO_FW_UPLOAD
103	bool "Cortina firmware loading support"
104	depends on PHY_CORTINA
105	help
106		Cortina phy has provision to store phy firmware in attached dedicated
107		EEPROM. And boards designed with such EEPROM does not require firmware
108		upload.
109
110choice
111	prompt "Location of the Cortina firmware"
112	default SYS_CORTINA_FW_IN_NOR
113	depends on PHY_CORTINA
114
115config SYS_CORTINA_FW_IN_MMC
116	bool "Cortina firmware in MMC"
117
118config SYS_CORTINA_FW_IN_NAND
119	bool "Cortina firmware in NAND flash"
120
121config SYS_CORTINA_FW_IN_NOR
122	bool "Cortina firmware in NOR flash"
123
124config SYS_CORTINA_FW_IN_REMOTE
125	bool "Cortina firmware in remote device"
126
127config SYS_CORTINA_FW_IN_SPIFLASH
128	bool "Cortina firmware in SPI flash"
129
130endchoice
131
132config CORTINA_FW_ADDR
133	hex "Cortina Firmware Address"
134	depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
135	default 0x0
136
137config CORTINA_FW_LENGTH
138	hex "Cortina Firmware Length"
139	depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
140	default 0x40000
141
142config PHY_CORTINA_ACCESS
143	bool "Cortina Access Ethernet PHYs support"
144	default y
145	depends on CORTINA_NI_ENET
146	help
147		Cortina Access Ethernet PHYs init process
148
149config PHY_DAVICOM
150	bool "Davicom Ethernet PHYs support"
151
152config PHY_ET1011C
153	bool "LSI TruePHY ET1011C support"
154
155config PHY_LXT
156	bool "LXT971 Ethernet PHY support"
157
158config PHY_MARVELL
159	bool "Marvell Ethernet PHYs support"
160
161config PHY_MESON_GXL
162	bool "Amlogic Meson GXL Internal PHY support"
163
164config PHY_MICREL
165	bool "Micrel Ethernet PHYs support"
166	help
167	  Enable support for the GbE PHYs manufactured by Micrel (now
168	  a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
169	  KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
170	  family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
171	  KSZ90x1 family support" is selected).
172
173if PHY_MICREL
174
175config PHY_MICREL_KSZ9021
176	bool
177	select PHY_MICREL_KSZ90X1
178
179config PHY_MICREL_KSZ9031
180	bool
181	select PHY_MICREL_KSZ90X1
182
183config PHY_MICREL_KSZ90X1
184	bool "Micrel KSZ90x1 family support"
185	select PHY_GIGE
186	help
187	  Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
188	  enabled, the extended register read/write for KSZ90x1 PHYs
189	  is supported through the 'mdio' command and any RGMII signal
190	  delays configured in the device tree will be applied to the
191	  PHY during initialization.
192
193config PHY_MICREL_KSZ8XXX
194	bool "Micrel KSZ8xxx family support"
195	help
196	  Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
197	  (now a part of Microchip). This includes drivers for the KSZ804,
198	  KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
199
200endif # PHY_MICREL
201
202config PHY_MSCC
203	bool "Microsemi Corp Ethernet PHYs support"
204
205config PHY_NATSEMI
206	bool "National Semiconductor Ethernet PHYs support"
207
208config PHY_NXP_C45_TJA11XX
209	tristate "NXP C45 TJA11XX PHYs"
210	help
211	  Enable support for NXP C45 TJA11XX PHYs.
212	  Currently supports only the TJA1103 PHY.
213
214config PHY_REALTEK
215	bool "Realtek Ethernet PHYs support"
216
217config RTL8211E_PINE64_GIGABIT_FIX
218	bool "Fix gigabit throughput on some Pine64+ models"
219	depends on PHY_REALTEK
220	help
221	  Configure the Realtek RTL8211E found on some Pine64+ models differently to
222	  fix throughput on Gigabit links, turning off all internal delays in the
223	  process. The settings that this touches are not documented in the CONFREG
224	  section of the RTL8211E datasheet, but come from Realtek by way of the
225	  Pine64 engineering team.
226
227config RTL8211X_PHY_FORCE_MASTER
228	bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
229	depends on PHY_REALTEK
230	help
231	  Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
232	  This can work around link stability and data corruption issues on gigabit
233	  links which can occur in slave mode on certain PHYs, e.g. on the
234	  RTL8211C(L).
235
236	  Please note that two directly connected devices (i.e. via crossover cable)
237	  will not be able to establish a link between each other if they both force
238	  master mode. Multiple devices forcing master mode when connected by a
239	  network switch do not pose a problem as the switch configures its affected
240	  ports into slave mode.
241
242	  This option only affects gigabit links. If you must establish a direct
243	  connection between two devices which both force master mode, try forcing
244	  the link speed to 100MBit/s.
245
246	  If unsure, say N.
247
248config RTL8211F_PHY_FORCE_EEE_RXC_ON
249	bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
250	depends on PHY_REALTEK
251	help
252	  The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
253	  transitions to/from a lower power consumption level (Low Power Idle
254	  mode) based on link utilization. When no packets are being
255	  transmitted, the system goes to Low Power Idle mode to save power.
256
257	  Under particular circumstances this setting can cause issues where
258	  the PHY is unable to transmit or receive any packet when in LPI mode.
259	  The problem is caused when the PHY is configured to stop receiving
260	  the xMII clock while it is signaling LPI. For some PHYs the bit
261	  configuring this behavior is set by the Linux kernel, causing the
262	  issue in U-Boot on reboot if the PHY retains the register value.
263
264	  Default n, which means that the PHY state is not changed. To work
265	  around the issues, change this setting to y.
266
267config RTL8201F_PHY_S700_RMII_TIMINGS
268	bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
269	depends on PHY_REALTEK
270	help
271	  This provides an option to configure specific timing requirements (needed
272	  for proper PHY operations) for the PHY module present on ACTION SEMI S700
273	  based cubieboard7. Exact timing requiremnets seems to be SoC specific
274	  (and it's undocumented) that comes from vendor code itself.
275
276config PHY_SMSC
277	bool  "Microchip(SMSC) Ethernet PHYs support"
278
279config PHY_TERANETICS
280	bool "Teranetics Ethernet PHYs support"
281
282config PHY_TI
283	bool "Texas Instruments Ethernet PHYs support"
284	---help---
285	  Adds PHY registration support for TI PHYs.
286
287config PHY_TI_DP83867
288	select PHY_TI
289	bool "Texas Instruments Ethernet DP83867 PHY support"
290	---help---
291	  Adds support for the TI DP83867 1Gbit PHY.
292
293config PHY_TI_GENERIC
294	select PHY_TI
295	bool "Texas Instruments Generic Ethernet PHYs support"
296	---help---
297	  Adds support for Generic TI PHYs that don't need special handling but
298	  the PHY name is associated with a PHY ID.
299
300config PHY_VITESSE
301	bool "Vitesse Ethernet PHYs support"
302
303config PHY_XILINX
304	bool "Xilinx Ethernet PHYs support"
305
306config PHY_XILINX_GMII2RGMII
307	bool "Xilinx GMII to RGMII Ethernet PHYs support"
308	depends on DM_ETH
309	help
310	  This adds support for Xilinx GMII to RGMII IP core. This IP acts
311	  as bridge between MAC connected over GMII and external phy that
312	  is connected over RGMII interface.
313
314config PHY_FIXED
315	bool "Fixed-Link PHY"
316	depends on DM_ETH
317	help
318	  Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
319	  connection (MII, RGMII, ...).
320	  There is nothing like autoneogation and so
321	  on, the link is always up with fixed speed and fixed duplex-setting.
322	  More information: doc/device-tree-bindings/net/fixed-link.txt
323
324config PHY_NCSI
325	bool "NC-SI based PHY"
326	depends on DM_ETH
327
328endif #PHYLIB
329