1if ARCH_SOCFPGA 2 3config ERR_PTR_OFFSET 4 default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range 5 6config NR_DRAM_BANKS 7 default 1 8 9config SOCFPGA_SECURE_VAB_AUTH 10 bool "Enable boot image authentication with Secure Device Manager" 11 depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X 12 select FIT_IMAGE_POST_PROCESS 13 select SHA384 14 select SHA512 15 select SPL_FIT_IMAGE_POST_PROCESS 16 help 17 All images loaded from FIT will be authenticated by Secure Device 18 Manager. 19 20config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE 21 bool "Allow non-FIT VAB signed images" 22 depends on SOCFPGA_SECURE_VAB_AUTH 23 24config SPL_SIZE_LIMIT 25 default 0x10000 if TARGET_SOCFPGA_GEN5 26 27config SPL_SIZE_LIMIT_PROVIDE_STACK 28 default 0x200 if TARGET_SOCFPGA_GEN5 29 30config SPL_STACK_R_ADDR 31 default 0x00800000 if TARGET_SOCFPGA_GEN5 32 33config SPL_SYS_MALLOC_F_LEN 34 default 0x800 if TARGET_SOCFPGA_GEN5 35 36config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 37 default 0xa2 38 39config SYS_MALLOC_F_LEN 40 default 0x2000 if TARGET_SOCFPGA_ARRIA10 41 default 0x2000 if TARGET_SOCFPGA_GEN5 42 43config SYS_TEXT_BASE 44 default 0x01000040 if TARGET_SOCFPGA_ARRIA10 45 default 0x01000040 if TARGET_SOCFPGA_GEN5 46 47config TARGET_SOCFPGA_AGILEX 48 bool 49 select ARMV8_MULTIENTRY 50 select ARMV8_SET_SMPEN 51 select BINMAN if SPL_ATF 52 select CLK 53 select FPGA_INTEL_SDM_MAILBOX 54 select NCORE_CACHE 55 select SPL_CLK if SPL 56 select TARGET_SOCFPGA_SOC64 57 58config TARGET_SOCFPGA_ARRIA5 59 bool 60 select TARGET_SOCFPGA_GEN5 61 62config TARGET_SOCFPGA_ARRIA10 63 bool 64 select SPL_ALTERA_SDRAM 65 select SPL_BOARD_INIT if SPL 66 select SPL_CACHE if SPL 67 select CLK 68 select SPL_CLK if SPL 69 select DM_I2C 70 select DM_RESET 71 select SPL_DM_RESET if SPL 72 select REGMAP 73 select SPL_REGMAP if SPL 74 select SYSCON 75 select SPL_SYSCON if SPL 76 select ETH_DESIGNWARE_SOCFPGA 77 imply FPGA_SOCFPGA 78 imply SPL_USE_TINY_PRINTF 79 80config TARGET_SOCFPGA_CYCLONE5 81 bool 82 select TARGET_SOCFPGA_GEN5 83 84config TARGET_SOCFPGA_GEN5 85 bool 86 select SPL_ALTERA_SDRAM 87 imply FPGA_SOCFPGA 88 imply SPL_SIZE_LIMIT_SUBTRACT_GD 89 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC 90 imply SPL_STACK_R 91 imply SPL_SYS_MALLOC_SIMPLE 92 imply SPL_USE_TINY_PRINTF 93 94config TARGET_SOCFPGA_N5X 95 bool 96 select ARMV8_MULTIENTRY 97 select ARMV8_SET_SMPEN 98 select BINMAN if SPL_ATF 99 select CLK 100 select FPGA_INTEL_SDM_MAILBOX 101 select NCORE_CACHE 102 select SPL_ALTERA_SDRAM 103 select SPL_CLK if SPL 104 select TARGET_SOCFPGA_SOC64 105 106config TARGET_SOCFPGA_N5X_SOCDK 107 bool "Intel eASIC SoCDK (N5X)" 108 select TARGET_SOCFPGA_N5X 109 110config TARGET_SOCFPGA_SOC64 111 bool 112 113config TARGET_SOCFPGA_STRATIX10 114 bool 115 select ARMV8_MULTIENTRY 116 select ARMV8_SET_SMPEN 117 select BINMAN if SPL_ATF 118 select FPGA_INTEL_SDM_MAILBOX 119 select TARGET_SOCFPGA_SOC64 120 121choice 122 prompt "Altera SOCFPGA board select" 123 optional 124 125config TARGET_SOCFPGA_AGILEX_SOCDK 126 bool "Intel SOCFPGA SoCDK (Agilex)" 127 select TARGET_SOCFPGA_AGILEX 128 129config TARGET_SOCFPGA_ARIES_MCVEVK 130 bool "Aries MCVEVK (Cyclone V)" 131 select TARGET_SOCFPGA_CYCLONE5 132 133config TARGET_SOCFPGA_ARRIA10_SOCDK 134 bool "Altera SOCFPGA SoCDK (Arria 10)" 135 select TARGET_SOCFPGA_ARRIA10 136 137config TARGET_SOCFPGA_ARRIA5_SECU1 138 bool "ABB SECU1 (Arria V)" 139 select TARGET_SOCFPGA_ARRIA5 140 select VENDOR_KM 141 142config TARGET_SOCFPGA_ARRIA5_SOCDK 143 bool "Altera SOCFPGA SoCDK (Arria V)" 144 select TARGET_SOCFPGA_ARRIA5 145 146config TARGET_SOCFPGA_CYCLONE5_SOCDK 147 bool "Altera SOCFPGA SoCDK (Cyclone V)" 148 select TARGET_SOCFPGA_CYCLONE5 149 150config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 151 bool "Devboards DBM-SoC1 (Cyclone V)" 152 select TARGET_SOCFPGA_CYCLONE5 153 154config TARGET_SOCFPGA_EBV_SOCRATES 155 bool "EBV SoCrates (Cyclone V)" 156 select TARGET_SOCFPGA_CYCLONE5 157 158config TARGET_SOCFPGA_IS1 159 bool "IS1 (Cyclone V)" 160 select TARGET_SOCFPGA_CYCLONE5 161 162config TARGET_SOCFPGA_SOFTING_VINING_FPGA 163 bool "Softing VIN|ING FPGA (Cyclone V)" 164 select BOARD_LATE_INIT 165 select TARGET_SOCFPGA_CYCLONE5 166 167config TARGET_SOCFPGA_SR1500 168 bool "SR1500 (Cyclone V)" 169 select TARGET_SOCFPGA_CYCLONE5 170 171config TARGET_SOCFPGA_STRATIX10_SOCDK 172 bool "Intel SOCFPGA SoCDK (Stratix 10)" 173 select TARGET_SOCFPGA_STRATIX10 174 175config TARGET_SOCFPGA_TERASIC_DE0_NANO 176 bool "Terasic DE0-Nano-Atlas (Cyclone V)" 177 select TARGET_SOCFPGA_CYCLONE5 178 179config TARGET_SOCFPGA_TERASIC_DE10_NANO 180 bool "Terasic DE10-Nano (Cyclone V)" 181 select TARGET_SOCFPGA_CYCLONE5 182 183config TARGET_SOCFPGA_TERASIC_DE1_SOC 184 bool "Terasic DE1-SoC (Cyclone V)" 185 select TARGET_SOCFPGA_CYCLONE5 186 187config TARGET_SOCFPGA_TERASIC_SOCKIT 188 bool "Terasic SoCkit (Cyclone V)" 189 select TARGET_SOCFPGA_CYCLONE5 190 191endchoice 192 193config SYS_BOARD 194 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK 195 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 196 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 197 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 198 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 199 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 200 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 201 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 202 default "is1" if TARGET_SOCFPGA_IS1 203 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 204 default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK 205 default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 206 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 207 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 208 default "sr1500" if TARGET_SOCFPGA_SR1500 209 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 210 default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA 211 212config SYS_VENDOR 213 default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK 214 default "intel" if TARGET_SOCFPGA_N5X_SOCDK 215 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 216 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 217 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 218 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK 219 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK 220 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 221 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 222 default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1 223 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA 224 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 225 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 226 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 227 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 228 229config SYS_SOC 230 default "socfpga" 231 232config SYS_CONFIG_NAME 233 default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK 234 default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 235 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 236 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 237 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 238 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 239 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 240 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 241 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 242 default "socfpga_is1" if TARGET_SOCFPGA_IS1 243 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 244 default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK 245 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 246 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 247 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 248 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 249 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA 250 251source "board/keymile/Kconfig" 252 253endif 254