1/*
2 * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef CPU_MACROS_S
7#define CPU_MACROS_S
8
9#include <arch.h>
10#include <assert_macros.S>
11#include <lib/cpus/errata_report.h>
12
13#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
14				(MIDR_PN_MASK << MIDR_PN_SHIFT)
15
16/* The number of CPU operations allowed */
17#define CPU_MAX_PWR_DWN_OPS		2
18
19/* Special constant to specify that CPU has no reset function */
20#define CPU_NO_RESET_FUNC		0
21
22#define CPU_NO_EXTRA1_FUNC		0
23#define CPU_NO_EXTRA2_FUNC		0
24#define CPU_NO_EXTRA3_FUNC		0
25
26/* Word size for 64-bit CPUs */
27#define CPU_WORD_SIZE			8
28
29/*
30 * Whether errata status needs reporting. Errata status is printed in debug
31 * builds for both BL1 and BL31 images.
32 */
33#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
34# define REPORT_ERRATA	1
35#else
36# define REPORT_ERRATA	0
37#endif
38
39
40	.equ	CPU_MIDR_SIZE, CPU_WORD_SIZE
41	.equ	CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
42	.equ	CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
43	.equ	CPU_EXTRA3_FUNC_SIZE, CPU_WORD_SIZE
44	.equ	CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE
45	.equ	CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
46	.equ	CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
47	.equ	CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
48	.equ	CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
49	.equ	CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
50	.equ	CPU_REG_DUMP_SIZE, CPU_WORD_SIZE
51
52#ifndef IMAGE_AT_EL3
53	.equ	CPU_RESET_FUNC_SIZE, 0
54#endif
55
56/* The power down core and cluster is needed only in BL31 */
57#ifndef IMAGE_BL31
58	.equ	CPU_PWR_DWN_OPS_SIZE, 0
59#endif
60
61/* Fields required to print errata status. */
62#if !REPORT_ERRATA
63	.equ	CPU_ERRATA_FUNC_SIZE, 0
64#endif
65
66/* Only BL31 requieres mutual exclusion and printed flag.  */
67#if !(REPORT_ERRATA && defined(IMAGE_BL31))
68	.equ	CPU_ERRATA_LOCK_SIZE, 0
69	.equ	CPU_ERRATA_PRINTED_SIZE, 0
70#endif
71
72#if !defined(IMAGE_BL31) || !CRASH_REPORTING
73	.equ	CPU_REG_DUMP_SIZE, 0
74#endif
75
76/*
77 * Define the offsets to the fields in cpu_ops structure.
78 * Every offset is defined based in the offset and size of the previous
79 * field.
80 */
81	.equ	CPU_MIDR, 0
82	.equ	CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
83	.equ	CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
84	.equ	CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
85	.equ	CPU_EXTRA3_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
86	.equ	CPU_E_HANDLER_FUNC, CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
87	.equ	CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
88	.equ	CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
89	.equ	CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
90	.equ	CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
91	.equ	CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
92	.equ	CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE
93
94	/*
95	 * Write given expressions as quad words
96	 *
97	 * _count:
98	 *	Write at least _count quad words. If the given number of
99	 *	expressions is less than _count, repeat the last expression to
100	 *	fill _count quad words in total
101	 * _rest:
102	 *	Optional list of expressions. _this is for parameter extraction
103	 *	only, and has no significance to the caller
104	 *
105	 * Invoked as:
106	 *	fill_constants 2, foo, bar, blah, ...
107	 */
108	.macro fill_constants _count:req, _this, _rest:vararg
109	  .ifgt \_count
110	    /* Write the current expression */
111	    .ifb \_this
112	      .error "Nothing to fill"
113	    .endif
114	    .quad \_this
115
116	    /* Invoke recursively for remaining expressions */
117	    .ifnb \_rest
118	      fill_constants \_count-1, \_rest
119	    .else
120	      fill_constants \_count-1, \_this
121	    .endif
122	  .endif
123	.endm
124
125	/*
126	 * Declare CPU operations
127	 *
128	 * _name:
129	 *	Name of the CPU for which operations are being specified
130	 * _midr:
131	 *	Numeric value expected to read from CPU's MIDR
132	 * _resetfunc:
133	 *	Reset function for the CPU. If there's no CPU reset function,
134	 *	specify CPU_NO_RESET_FUNC
135	 * _extra1:
136	 *	This is a placeholder for future per CPU operations.  Currently,
137	 *	some CPUs use this entry to set a test function to determine if
138	 *	the workaround for CVE-2017-5715 needs to be applied or not.
139	 * _extra2:
140	 *	This is a placeholder for future per CPU operations. Currently
141	 *	some CPUs use this entry to set a function to disable the
142	 *	workaround for CVE-2018-3639.
143	 * _extra3:
144	 *	This is a placeholder for future per CPU operations. Currently,
145	 *	some CPUs use this entry to set a test function to determine if
146	 *	the workaround for CVE-2022-23960 needs to be applied or not.
147	 * _e_handler:
148	 *	This is a placeholder for future per CPU exception handlers.
149	 * _power_down_ops:
150	 *	Comma-separated list of functions to perform power-down
151	 *	operatios on the CPU. At least one, and up to
152	 *	CPU_MAX_PWR_DWN_OPS number of functions may be specified.
153	 *	Starting at power level 0, these functions shall handle power
154	 *	down at subsequent power levels. If there aren't exactly
155	 *	CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
156	 *	used to handle power down at subsequent levels
157	 */
158	.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
159		_extra1:req, _extra2:req, _extra3:req, _e_handler:req, _power_down_ops:vararg
160	.section cpu_ops, "a"
161	.align 3
162	.type cpu_ops_\_name, %object
163	.quad \_midr
164#if defined(IMAGE_AT_EL3)
165	.quad \_resetfunc
166#endif
167	.quad \_extra1
168	.quad \_extra2
169	.quad \_extra3
170	.quad \_e_handler
171#ifdef IMAGE_BL31
172	/* Insert list of functions */
173	fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
174#endif
175
176#if REPORT_ERRATA
177	.ifndef \_name\()_cpu_str
178	  /*
179	   * Place errata reported flag, and the spinlock to arbitrate access to
180	   * it in the data section.
181	   */
182	  .pushsection .data
183	  define_asm_spinlock \_name\()_errata_lock
184	  \_name\()_errata_reported:
185	  .word	0
186	  .popsection
187
188	  /* Place CPU string in rodata */
189	  .pushsection .rodata
190	  \_name\()_cpu_str:
191	  .asciz "\_name"
192	  .popsection
193	.endif
194
195	/*
196	 * Mandatory errata status printing function for CPUs of
197	 * this class.
198	 */
199	.quad \_name\()_errata_report
200
201#ifdef IMAGE_BL31
202	/* Pointers to errata lock and reported flag */
203	.quad \_name\()_errata_lock
204	.quad \_name\()_errata_reported
205#endif
206#endif
207
208#if defined(IMAGE_BL31) && CRASH_REPORTING
209	.quad \_name\()_cpu_reg_dump
210#endif
211	.endm
212
213	.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
214		_power_down_ops:vararg
215		declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, \
216			\_power_down_ops
217	.endm
218
219	.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
220		_e_handler:req, _power_down_ops:vararg
221		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
222			0, 0, 0, \_e_handler, \_power_down_ops
223	.endm
224
225	.macro declare_cpu_ops_wa _name:req, _midr:req, \
226		_resetfunc:req, _extra1:req, _extra2:req, \
227		_extra3:req, _power_down_ops:vararg
228		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
229			\_extra1, \_extra2, \_extra3, 0, \_power_down_ops
230	.endm
231
232#if REPORT_ERRATA
233	/*
234	 * Print status of a CPU errata
235	 *
236	 * _chosen:
237	 *	Identifier indicating whether or not a CPU errata has been
238	 *	compiled in.
239	 * _cpu:
240	 *	Name of the CPU
241	 * _id:
242	 *	Errata identifier
243	 * _rev_var:
244	 *	Register containing the combined value CPU revision and variant
245	 *	- typically the return value of cpu_get_rev_var
246	 */
247	.macro report_errata _chosen, _cpu, _id, _rev_var=x8
248	/* Stash a string with errata ID */
249	.pushsection .rodata
250	\_cpu\()_errata_\_id\()_str:
251	.asciz	"\_id"
252	.popsection
253
254	/* Check whether errata applies */
255	mov	x0, \_rev_var
256	/* Shall clobber: x0-x7 */
257	bl	check_errata_\_id
258
259	.ifeq \_chosen
260	/*
261	 * Errata workaround has not been compiled in. If the errata would have
262	 * applied had it been compiled in, print its status as missing.
263	 */
264	cbz	x0, 900f
265	mov	x0, #ERRATA_MISSING
266	.endif
267900:
268	adr	x1, \_cpu\()_cpu_str
269	adr	x2, \_cpu\()_errata_\_id\()_str
270	bl	errata_print_msg
271	.endm
272#endif
273
274	/*
275	 * This macro is used on some CPUs to detect if they are vulnerable
276	 * to CVE-2017-5715.
277	 */
278	.macro	cpu_check_csv2 _reg _label
279	mrs	\_reg, id_aa64pfr0_el1
280	ubfx	\_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
281	/*
282	 * If the field equals 1, branch targets trained in one context cannot
283	 * affect speculative execution in a different context.
284	 *
285	 * If the field equals 2, it means that the system is also aware of
286	 * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
287	 * expect users of the registers to do the right thing.
288	 *
289	 * Only apply mitigations if the value of this field is 0.
290	 */
291#if ENABLE_ASSERTIONS
292	cmp	\_reg, #3 /* Only values 0 to 2 are expected */
293	ASM_ASSERT(lo)
294#endif
295
296	cmp	\_reg, #0
297	bne	\_label
298	.endm
299
300	/*
301	 * Helper macro that reads the part number of the current
302	 * CPU and jumps to the given label if it matches the CPU
303	 * MIDR provided.
304	 *
305	 * Clobbers x0.
306	 */
307	.macro  jump_if_cpu_midr _cpu_midr, _label
308	mrs	x0, midr_el1
309	ubfx	x0, x0, MIDR_PN_SHIFT, #12
310	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
311	b.eq	\_label
312	.endm
313
314#endif /* CPU_MACROS_S */
315