1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX_CSU_H 8 #define IMX_CSU_H 9 10 #include <lib/utils_def.h> 11 12 #include <platform_def.h> 13 14 #define CSU_SEC_LEVEL_0 0xff 15 #define CSU_SEC_LEVEL_1 0xbb 16 #define CSU_SEC_LEVEL_2 0x3f 17 #define CSU_SEC_LEVEL_3 0x3b 18 #define CSU_SEC_LEVEL_4 0x33 19 #define CSU_SEC_LEVEL_5 0x22 20 #define CSU_SEC_LEVEL_6 0x03 21 #define CSU_SEC_LEVEL_7 0x0 22 23 #define LOCKED 0x1 24 #define UNLOCKED 0x0 25 26 #define CSLx_REG(x) (IMX_CSU_BASE + ((x) / 2) * 4) 27 #define CSLx_LOCK(x) ((0x1 << (((x) % 2) * 16 + 8))) 28 #define CSLx_CFG(x, n) ((x) << (((n) % 2) * 16)) 29 30 #define CSU_HP_REG(x) (IMX_CSU_BASE + ((x) / 16) * 4 + 0x200) 31 #define CSU_HP_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) 32 #define CSU_HP_CFG(x, n) ((x) << (((n) % 16) * 2)) 33 34 #define CSU_SA_REG(x) (IMX_CSU_BASE + 0x218) 35 #define CSU_SA_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) 36 #define CSU_SA_CFG(x, n) ((x) << (((n) % 16) * 2)) 37 38 #define CSU_HPCONTROL_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x358) 39 #define CSU_HPCONTROL_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) 40 #define CSU_HPCONTROL_CFG(x, n) ((x) << (((n) % 16) * 2)) 41 42 enum csu_cfg_type { 43 CSU_INVALID, 44 CSU_CSL, 45 CSU_HP, 46 CSU_SA, 47 CSU_HPCONTROL, 48 }; 49 50 struct imx_csu_cfg { 51 enum csu_cfg_type type; 52 uint16_t idx; 53 uint16_t lock : 1; 54 uint16_t csl_level : 8; 55 uint16_t hp : 1; 56 uint16_t sa : 1; 57 uint16_t hpctrl : 1; 58 }; 59 60 #define CSU_CSLx(i, level, lk) \ 61 {CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),} 62 63 #define CSU_HPx(i, val, lk) \ 64 {CSU_HP, .idx = (i), .hp = (val), .lock = (lk), } 65 66 #define CSU_SA(i, val, lk) \ 67 {CSU_SA, .idx = (i), .sa = (val), .lock = (lk), } 68 69 #define CSU_HPCTRL(i, val, lk) \ 70 {CSU_HPCONTROL, .idx = (i), .hpctrl = (val), .lock = (lk), } 71 72 void imx_csu_init(const struct imx_csu_cfg *csu_cfg); 73 74 #endif /* IMX_CSU_H */ 75