Home
last modified time | relevance | path

Searched defs:CTRL (Results 1 – 25 of 99) sorted by relevance

1234

/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/cmsis/
A Dreg_patch.h13 __IO uint32_t CTRL[PATCH_ENTRY_NUM]; member
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Drtl8721d_ir.h261 #define IS_IR_RX_FILTER_TIME_CTRL(CTRL) (((CTRL) == IR_RX_FILTER_TIME_20NS) || \ argument
280 #define IS_IR_RX_FIFO_FULL_DISCARD_CTRL(CTRL) (((CTRL) == IR_RX_FIFO_FULL_DISCARD_NEWEST) || \ argument
320 #define IS_IR_RX_COUNT_LEVEL_CTRL(CTRL) (((CTRL) == IR_RX_COUNT_LOW_LEVEL) || \ argument
A Drtl8721d_keyscan.h145 #define IS_KS_FIFO_OVER_CTRL(CTRL) (((CTRL) == KS_FIFO_OVER_CTRL_DIS_NEW) || \ argument
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/hal/
A Dreg_transq.h13 __IO uint32_t CTRL; // 0x000 member
A Dreg_dma.h32 __IO uint32_t CTRL; // 0x210+N*0x20 DMA 2D Control Register member
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/cmsis/
A Dcore_cm0plus.h433 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
484 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
A Dcore_armv8mbl.h644 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
696 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
968 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1067 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/cmsis/inc/
A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
A Dcore_cm23.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/AliOS-Things-master/components/csi/CMSIS/Core/Include/
A Dcore_sc000.h490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_armv8mbl.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/AliOS-Things-master/components/py_engine/engine/lib/cmsis/inc/
A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_sc000.h485 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_armv8mbl.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
A Dcore_cm23.h560 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
902 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1008 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/third_party/cmsis/CMSIS/Core/Include/
A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_sc000.h490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_armv8mbl.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/tensorflow/lite/micro/tools/make/downloads/cmsis/CMSIS/Core/Include/
A Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_sc000.h490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
A Dcore_armv8mbl.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/AliOS-Things-master/hardware/chip/haas1000/drivers/services/ble_stack/hci/src/
A Dhci_int.h111 CTRL, enumerator

Completed in 143 milliseconds

1234