1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #ifndef R8180_HW 8 #define R8180_HW 9 10 enum baseband_config { 11 BB_CONFIG_PHY_REG = 0, 12 BB_CONFIG_AGC_TAB = 1, 13 }; 14 15 #define RTL8190_EEPROM_ID 0x8129 16 #define EEPROM_VID 0x02 17 #define EEPROM_DID 0x04 18 #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C 19 20 #define EEPROM_Default_ThermalMeter 0x77 21 #define EEPROM_Default_AntTxPowerDiff 0x0 22 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5 23 #define EEPROM_Default_TxPower 0x1010 24 #define EEPROM_ICVersion_ChannelPlan 0x7C 25 #define EEPROM_Customer_ID 0x7B 26 #define EEPROM_RFInd_PowerDiff 0x28 27 28 #define EEPROM_ThermalMeter 0x29 29 #define EEPROM_TxPwDiff_CrystalCap 0x2A 30 #define EEPROM_TxPwIndex_CCK 0x2C 31 #define EEPROM_TxPwIndex_OFDM_24G 0x3A 32 33 #define EEPROM_CID_DEFAULT 0x0 34 #define EEPROM_CID_CAMEO 0x1 35 #define EEPROM_CID_RUNTOP 0x2 36 #define EEPROM_CID_TOSHIBA 0x4 37 #define EEPROM_CID_NetCore 0x5 38 #define EEPROM_CID_Nettronix 0x6 39 #define EEPROM_CID_Pronet 0x7 40 #define EEPROM_CID_DLINK 0x8 41 #define EEPROM_CID_WHQL 0xFE 42 enum _RTL8192PCI_HW { 43 MAC0 = 0x000, 44 MAC4 = 0x004, 45 PCIF = 0x009, 46 #define MXDMA2_NO_LIMIT 0x7 47 48 #define MXDMA2_RX_SHIFT 4 49 #define MXDMA2_TX_SHIFT 0 50 PMR = 0x00c, 51 EPROM_CMD = 0x00e, 52 53 #define EPROM_CMD_9356SEL BIT4 54 #define EPROM_CMD_OPERATING_MODE_SHIFT 6 55 #define EPROM_CMD_NORMAL 0 56 #define EPROM_CMD_PROGRAM 2 57 #define EPROM_CS_BIT 3 58 #define EPROM_CK_BIT 2 59 #define EPROM_W_BIT 1 60 #define EPROM_R_BIT 0 61 62 ANAPAR = 0x17, 63 #define BB_GLOBAL_RESET_BIT 0x1 64 BB_GLOBAL_RESET = 0x020, 65 BSSIDR = 0x02E, 66 CMDR = 0x037, 67 #define CR_RE 0x08 68 #define CR_TE 0x04 69 SIFS = 0x03E, 70 RCR = 0x044, 71 #define RCR_ONLYERLPKT BIT31 72 #define RCR_CBSSID BIT23 73 #define RCR_ADD3 BIT21 74 #define RCR_AMF BIT20 75 #define RCR_ADF BIT18 76 #define RCR_AICV BIT12 77 #define RCR_AB BIT3 78 #define RCR_AM BIT2 79 #define RCR_APM BIT1 80 #define RCR_AAP BIT0 81 #define RCR_MXDMA_OFFSET 8 82 #define RCR_FIFO_OFFSET 13 83 SLOT_TIME = 0x049, 84 ACK_TIMEOUT = 0x04c, 85 EDCAPARA_BE = 0x050, 86 EDCAPARA_BK = 0x054, 87 EDCAPARA_VO = 0x058, 88 EDCAPARA_VI = 0x05C, 89 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 90 #define AC_PARAM_ECW_MAX_OFFSET 12 91 #define AC_PARAM_ECW_MIN_OFFSET 8 92 #define AC_PARAM_AIFS_OFFSET 0 93 BCN_TCFG = 0x062, 94 #define BCN_TCFG_CW_SHIFT 8 95 #define BCN_TCFG_IFS 0 96 BCN_INTERVAL = 0x070, 97 ATIMWND = 0x072, 98 BCN_DRV_EARLY_INT = 0x074, 99 BCN_DMATIME = 0x076, 100 BCN_ERR_THRESH = 0x078, 101 RWCAM = 0x0A0, 102 #define TOTAL_CAM_ENTRY 32 103 WCAMI = 0x0A4, 104 SECR = 0x0B0, 105 #define SCR_TxUseDK BIT0 106 #define SCR_RxUseDK BIT1 107 #define SCR_TxEncEnable BIT2 108 #define SCR_RxDecEnable BIT3 109 #define SCR_NoSKMC BIT5 110 SWREGULATOR = 0x0BD, 111 INTA_MASK = 0x0f4, 112 #define IMR_TBDOK BIT27 113 #define IMR_TBDER BIT26 114 #define IMR_TXFOVW BIT15 115 #define IMR_TIMEOUT0 BIT14 116 #define IMR_BcnInt BIT13 117 #define IMR_RXFOVW BIT12 118 #define IMR_RDU BIT11 119 #define IMR_RXCMDOK BIT10 120 #define IMR_BDOK BIT9 121 #define IMR_HIGHDOK BIT8 122 #define IMR_COMDOK BIT7 123 #define IMR_MGNTDOK BIT6 124 #define IMR_HCCADOK BIT5 125 #define IMR_BKDOK BIT4 126 #define IMR_BEDOK BIT3 127 #define IMR_VIDOK BIT2 128 #define IMR_VODOK BIT1 129 #define IMR_ROK BIT0 130 ISR = 0x0f8, 131 TP_POLL = 0x0fd, 132 #define TP_POLL_CQ BIT5 133 PSR = 0x0ff, 134 CPU_GEN = 0x100, 135 #define CPU_CCK_LOOPBACK 0x00030000 136 #define CPU_GEN_SYSTEM_RESET 0x00000001 137 #define CPU_GEN_FIRMWARE_RESET 0x00000008 138 #define CPU_GEN_BOOT_RDY 0x00000010 139 #define CPU_GEN_FIRM_RDY 0x00000020 140 #define CPU_GEN_PUT_CODE_OK 0x00000080 141 #define CPU_GEN_BB_RST 0x00000100 142 #define CPU_GEN_PWR_STB_CPU 0x00000004 143 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF 144 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 145 ACM_HW_CTRL = 0x171, 146 #define ACM_HW_BEQ_EN BIT1 147 #define ACM_HW_VIQ_EN BIT2 148 #define ACM_HW_VOQ_EN BIT3 149 RQPN1 = 0x180, 150 RQPN2 = 0x184, 151 RQPN3 = 0x188, 152 QPNR = 0x1F0, 153 BQDA = 0x200, 154 HQDA = 0x204, 155 CQDA = 0x208, 156 MQDA = 0x20C, 157 HCCAQDA = 0x210, 158 VOQDA = 0x214, 159 VIQDA = 0x218, 160 BEQDA = 0x21C, 161 BKQDA = 0x220, 162 RDQDA = 0x228, 163 164 WFCRC0 = 0x2f0, 165 WFCRC1 = 0x2f4, 166 WFCRC2 = 0x2f8, 167 168 BW_OPMODE = 0x300, 169 #define BW_OPMODE_5G BIT1 170 #define BW_OPMODE_20MHZ BIT2 171 IC_VERRSION = 0x301, 172 MSR = 0x303, 173 #define MSR_LINK_MASK (BIT(1) | BIT(0)) 174 #define MSR_LINK_MANAGED 2 175 #define MSR_LINK_ADHOC 1 176 #define MSR_LINK_MASTER 3 177 178 #define MSR_NOLINK 0x00 179 #define MSR_ADHOC 0x01 180 #define MSR_INFRA 0x02 181 #define MSR_AP 0x03 182 183 RETRY_LIMIT = 0x304, 184 #define RETRY_LIMIT_SHORT_SHIFT 8 185 #define RETRY_LIMIT_LONG_SHIFT 0 186 TSFR = 0x308, 187 RRSR = 0x310, 188 #define RRSR_SHORT_OFFSET 23 189 #define RRSR_1M BIT0 190 #define RRSR_2M BIT1 191 #define RRSR_5_5M BIT2 192 #define RRSR_11M BIT3 193 #define RRSR_6M BIT4 194 #define RRSR_9M BIT5 195 #define RRSR_12M BIT6 196 #define RRSR_18M BIT7 197 #define RRSR_24M BIT8 198 #define RRSR_36M BIT9 199 #define RRSR_48M BIT10 200 #define RRSR_54M BIT11 201 #define BRSR_AckShortPmb BIT23 202 UFWP = 0x318, 203 RATR0 = 0x320, 204 #define RATR_1M 0x00000001 205 #define RATR_2M 0x00000002 206 #define RATR_55M 0x00000004 207 #define RATR_11M 0x00000008 208 #define RATR_6M 0x00000010 209 #define RATR_9M 0x00000020 210 #define RATR_12M 0x00000040 211 #define RATR_18M 0x00000080 212 #define RATR_24M 0x00000100 213 #define RATR_36M 0x00000200 214 #define RATR_48M 0x00000400 215 #define RATR_54M 0x00000800 216 #define RATR_MCS0 0x00001000 217 #define RATR_MCS1 0x00002000 218 #define RATR_MCS2 0x00004000 219 #define RATR_MCS3 0x00008000 220 #define RATR_MCS4 0x00010000 221 #define RATR_MCS5 0x00020000 222 #define RATR_MCS6 0x00040000 223 #define RATR_MCS7 0x00080000 224 #define RATR_MCS8 0x00100000 225 #define RATR_MCS9 0x00200000 226 #define RATR_MCS10 0x00400000 227 #define RATR_MCS11 0x00800000 228 #define RATR_MCS12 0x01000000 229 #define RATR_MCS13 0x02000000 230 #define RATR_MCS14 0x04000000 231 #define RATR_MCS15 0x08000000 232 #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 233 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \ 234 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 235 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 236 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 237 RATR_MCS6 | RATR_MCS7) 238 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 239 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 240 RATR_MCS14|RATR_MCS15) 241 242 DRIVER_RSSI = 0x32c, 243 MCS_TXAGC = 0x340, 244 CCK_TXAGC = 0x348, 245 MAC_BLK_CTRL = 0x403, 246 }; 247 248 #define GPI 0x108 249 250 #define ANAPAR_FOR_8192PCIE 0x17 251 252 #endif 253