1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_cortex.h
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 25-June-2015
7 * @brief Header file of CORTEX HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_CORTEX_H
40 #define __STM32F7xx_HAL_CORTEX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup CORTEX
54 * @{
55 */
56 /* Exported types ------------------------------------------------------------*/
57 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
58 * @{
59 */
60
61 #if (__MPU_PRESENT == 1)
62 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
63 * @brief MPU Region initialization structure
64 * @{
65 */
66 typedef struct {
67 uint8_t Enable; /*!< Specifies the status of the region.
68 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
69 uint8_t Number; /*!< Specifies the number of the region to protect.
70 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
71 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
72 uint8_t Size; /*!< Specifies the size of the region to protect.
73 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
74 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
75 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
76 uint8_t TypeExtField; /*!< Specifies the TEX field level.
77 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
78 uint8_t AccessPermission; /*!< Specifies the region access permission type.
79 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
80 uint8_t DisableExec; /*!< Specifies the instruction access status.
81 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
82 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
83 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
84 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
85 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
86 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
87 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
88 } MPU_Region_InitTypeDef;
89 /**
90 * @}
91 */
92 #endif /* __MPU_PRESENT */
93
94 /**
95 * @}
96 */
97
98 /* Exported constants --------------------------------------------------------*/
99
100 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
101 * @{
102 */
103
104 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
105 * @{
106 */
107 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
108 4 bits for subpriority */
109 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
110 3 bits for subpriority */
111 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
112 2 bits for subpriority */
113 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
114 1 bits for subpriority */
115 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
116 0 bits for subpriority */
117 /**
118 * @}
119 */
120
121 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
122 * @{
123 */
124 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
125 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
126
127 /**
128 * @}
129 */
130
131 #if (__MPU_PRESENT == 1)
132 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
133 * @{
134 */
135 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
136 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
137 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
138 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
139 /**
140 * @}
141 */
142
143 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
144 * @{
145 */
146 #define MPU_REGION_ENABLE ((uint8_t)0x01)
147 #define MPU_REGION_DISABLE ((uint8_t)0x00)
148 /**
149 * @}
150 */
151
152 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
153 * @{
154 */
155 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
156 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
157 /**
158 * @}
159 */
160
161 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
162 * @{
163 */
164 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
165 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
166 /**
167 * @}
168 */
169
170 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
171 * @{
172 */
173 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
174 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
175 /**
176 * @}
177 */
178
179 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
180 * @{
181 */
182 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
183 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
184 /**
185 * @}
186 */
187
188 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
189 * @{
190 */
191 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
192 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
193 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
194 /**
195 * @}
196 */
197
198 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
199 * @{
200 */
201 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
202 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
203 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
204 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
205 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
206 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
207 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
208 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
209 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
210 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
211 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
212 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
213 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
214 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
215 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
216 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
217 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
218 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
219 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
220 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
221 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
222 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
223 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
224 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
225 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
226 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
227 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
228 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
229 /**
230 * @}
231 */
232
233 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
234 * @{
235 */
236 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
237 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
238 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
239 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
240 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
241 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
242 /**
243 * @}
244 */
245
246 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
247 * @{
248 */
249 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
250 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
251 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
252 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
253 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
254 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
255 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
256 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
257 /**
258 * @}
259 */
260 #endif /* __MPU_PRESENT */
261
262 /**
263 * @}
264 */
265
266
267 /* Exported Macros -----------------------------------------------------------*/
268 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
269 * @{
270 */
271
272 /** @brief Configures the SysTick clock source.
273 * @param __CLKSRC__: specifies the SysTick clock source.
274 * This parameter can be one of the following values:
275 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
276 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
277 * @retval None
278 */
279 #define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
280 do { \
281 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
282 { \
283 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
284 } \
285 else \
286 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
287 } while(0)
288 /**
289 * @}
290 */
291
292 /* Exported functions --------------------------------------------------------*/
293 /** @addtogroup CORTEX_Exported_Functions
294 * @{
295 */
296
297 /** @addtogroup CORTEX_Exported_Functions_Group1
298 * @{
299 */
300 /* Initialization and de-initialization functions *****************************/
301 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
302 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
303 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
304 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
305 void HAL_NVIC_SystemReset(void);
306 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
307 /**
308 * @}
309 */
310
311 /** @addtogroup CORTEX_Exported_Functions_Group2
312 * @{
313 */
314 /* Peripheral Control functions ***********************************************/
315 #if (__MPU_PRESENT == 1)
316 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
317 #endif /* __MPU_PRESENT */
318 uint32_t HAL_NVIC_GetPriorityGrouping(void);
319 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
320 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
321 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
322 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
323 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
324 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
325 void HAL_SYSTICK_IRQHandler(void);
326 void HAL_SYSTICK_Callback(void);
327 /**
328 * @}
329 */
330
331 /**
332 * @}
333 */
334
335 /* Private types -------------------------------------------------------------*/
336 /* Private variables ---------------------------------------------------------*/
337 /* Private constants ---------------------------------------------------------*/
338 /* Private macros ------------------------------------------------------------*/
339 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
340 * @{
341 */
342 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
343 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
344 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
345 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
346 ((GROUP) == NVIC_PRIORITYGROUP_4))
347
348 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
349
350 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
351
352 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
353
354 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
355 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
356
357 #if (__MPU_PRESENT == 1)
358 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
359 ((STATE) == MPU_REGION_DISABLE))
360
361 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
362 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
363
364 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
365 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
366
367 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
368 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
369
370 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
371 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
372
373 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
374 ((TYPE) == MPU_TEX_LEVEL1) || \
375 ((TYPE) == MPU_TEX_LEVEL2))
376
377 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
378 ((TYPE) == MPU_REGION_PRIV_RW) || \
379 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
380 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
381 ((TYPE) == MPU_REGION_PRIV_RO) || \
382 ((TYPE) == MPU_REGION_PRIV_RO_URO))
383
384 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
385 ((NUMBER) == MPU_REGION_NUMBER1) || \
386 ((NUMBER) == MPU_REGION_NUMBER2) || \
387 ((NUMBER) == MPU_REGION_NUMBER3) || \
388 ((NUMBER) == MPU_REGION_NUMBER4) || \
389 ((NUMBER) == MPU_REGION_NUMBER5) || \
390 ((NUMBER) == MPU_REGION_NUMBER6) || \
391 ((NUMBER) == MPU_REGION_NUMBER7))
392
393 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
394 ((SIZE) == MPU_REGION_SIZE_64B) || \
395 ((SIZE) == MPU_REGION_SIZE_128B) || \
396 ((SIZE) == MPU_REGION_SIZE_256B) || \
397 ((SIZE) == MPU_REGION_SIZE_512B) || \
398 ((SIZE) == MPU_REGION_SIZE_1KB) || \
399 ((SIZE) == MPU_REGION_SIZE_2KB) || \
400 ((SIZE) == MPU_REGION_SIZE_4KB) || \
401 ((SIZE) == MPU_REGION_SIZE_8KB) || \
402 ((SIZE) == MPU_REGION_SIZE_16KB) || \
403 ((SIZE) == MPU_REGION_SIZE_32KB) || \
404 ((SIZE) == MPU_REGION_SIZE_64KB) || \
405 ((SIZE) == MPU_REGION_SIZE_128KB) || \
406 ((SIZE) == MPU_REGION_SIZE_256KB) || \
407 ((SIZE) == MPU_REGION_SIZE_512KB) || \
408 ((SIZE) == MPU_REGION_SIZE_1MB) || \
409 ((SIZE) == MPU_REGION_SIZE_2MB) || \
410 ((SIZE) == MPU_REGION_SIZE_4MB) || \
411 ((SIZE) == MPU_REGION_SIZE_8MB) || \
412 ((SIZE) == MPU_REGION_SIZE_16MB) || \
413 ((SIZE) == MPU_REGION_SIZE_32MB) || \
414 ((SIZE) == MPU_REGION_SIZE_64MB) || \
415 ((SIZE) == MPU_REGION_SIZE_128MB) || \
416 ((SIZE) == MPU_REGION_SIZE_256MB) || \
417 ((SIZE) == MPU_REGION_SIZE_512MB) || \
418 ((SIZE) == MPU_REGION_SIZE_1GB) || \
419 ((SIZE) == MPU_REGION_SIZE_2GB) || \
420 ((SIZE) == MPU_REGION_SIZE_4GB))
421
422 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
423 #endif /* __MPU_PRESENT */
424
425 /**
426 * @}
427 */
428
429 /* Private functions ---------------------------------------------------------*/
430 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
431 * @brief CORTEX private functions
432 * @{
433 */
434
435 #if (__MPU_PRESENT == 1)
436 /**
437 * @brief Disables the MPU
438 * @retval None
439 */
HAL_MPU_Disable(void)440 __STATIC_INLINE void HAL_MPU_Disable(void)
441 {
442 /* Disable fault exceptions */
443 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
444
445 /* Disable the MPU */
446 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
447 }
448
449 /**
450 * @brief Enables the MPU
451 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
452 * NMI, FAULTMASK and privileged access to the default memory
453 * This parameter can be one of the following values:
454 * @arg MPU_HFNMI_PRIVDEF_NONE
455 * @arg MPU_HARDFAULT_NMI
456 * @arg MPU_PRIVILEGED_DEFAULT
457 * @arg MPU_HFNMI_PRIVDEF
458 * @retval None
459 */
HAL_MPU_Enable(uint32_t MPU_Control)460 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
461 {
462 /* Enable the MPU */
463 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
464
465 /* Enable fault exceptions */
466 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
467 }
468 #endif /* __MPU_PRESENT */
469
470 /**
471 * @}
472 */
473
474 /**
475 * @}
476 */
477
478 /**
479 * @}
480 */
481
482 #ifdef __cplusplus
483 }
484 #endif
485
486 #endif /* __STM32F7xx_HAL_CORTEX_H */
487
488
489 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
490