1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016-2018, 2020 NXP 4 * Copyright 2015, Freescale Semiconductor 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #ifndef __ASSEMBLY__ 14 #include <linux/bitops.h> 15 #endif 16 17 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 18 19 /* 20 * Reserve secure memory 21 * To be aligned with MMU block size 22 */ 23 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ 24 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ 25 26 #ifdef CONFIG_ARCH_LS2080A 27 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 28 #define SRDS_MAX_LANES 8 29 #define CONFIG_SYS_PAGE_SIZE 0x10000 30 #ifndef L1_CACHE_BYTES 31 #define L1_CACHE_SHIFT 6 32 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 33 #endif 34 35 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 36 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 37 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 38 39 /* DDR */ 40 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 41 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 42 43 #define CONFIG_SYS_FSL_CCSR_GUR_LE 44 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 45 #define CONFIG_SYS_FSL_ESDHC_LE 46 #define CONFIG_SYS_FSL_IFC_LE 47 #define CONFIG_SYS_FSL_PEX_LUT_LE 48 49 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 50 51 /* Generic Interrupt Controller Definitions */ 52 #define GICD_BASE 0x06000000 53 #define GICR_BASE 0x06100000 54 55 /* SMMU Defintions */ 56 #define SMMU_BASE 0x05000000 /* GR0 Base */ 57 58 /* SFP */ 59 #define CONFIG_SYS_FSL_SFP_VER_3_4 60 #define CONFIG_SYS_FSL_SFP_LE 61 #define CONFIG_SYS_FSL_SRK_LE 62 63 /* Security Monitor */ 64 #define CONFIG_SYS_FSL_SEC_MON_LE 65 66 /* Secure Boot */ 67 #define CONFIG_ESBC_HDR_LS 68 69 /* DCFG - GUR */ 70 #define CONFIG_SYS_FSL_CCSR_GUR_LE 71 72 /* Cache Coherent Interconnect */ 73 #define CCI_MN_BASE 0x04000000 74 #define CCI_MN_RNF_NODEID_LIST 0x180 75 #define CCI_MN_DVM_DOMAIN_CTL 0x200 76 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 77 78 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 79 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 80 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 81 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 82 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 83 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 84 85 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 86 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 87 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 88 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 89 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 90 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 91 92 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 93 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 94 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 95 96 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 97 98 /* TZ Protection Controller Definitions */ 99 #define TZPC_BASE 0x02200000 100 #define TZPCR0SIZE_BASE (TZPC_BASE) 101 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 102 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 103 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 104 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 105 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 106 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 107 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 108 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 109 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 110 111 #define DCSR_CGACRE5 0x700070914ULL 112 #define EPU_EPCMPR5 0x700060914ULL 113 #define EPU_EPCCR5 0x700060814ULL 114 #define EPU_EPSMCR5 0x700060228ULL 115 #define EPU_EPECR5 0x700060314ULL 116 #define EPU_EPCTR5 0x700060a14ULL 117 #define EPU_EPGCR 0x700060000ULL 118 119 #define CONFIG_SYS_FSL_ERRATUM_A008751 120 121 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 122 123 #elif defined(CONFIG_ARCH_LS1088A) 124 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 125 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 126 #define CONFIG_SYS_PAGE_SIZE 0x10000 127 128 #define SRDS_MAX_LANES 4 129 #define SRDS_BITS_PER_LANE 4 130 131 /* TZ Protection Controller Definitions */ 132 #define TZPC_BASE 0x02200000 133 #define TZPCR0SIZE_BASE (TZPC_BASE) 134 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 135 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 136 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 137 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 138 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 139 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 140 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 141 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 142 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 143 144 /* Generic Interrupt Controller Definitions */ 145 #define GICD_BASE 0x06000000 146 #define GICR_BASE 0x06100000 147 148 /* SMMU Defintions */ 149 #define SMMU_BASE 0x05000000 /* GR0 Base */ 150 151 /* DDR */ 152 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 153 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 154 155 #define CONFIG_SYS_FSL_CCSR_GUR_LE 156 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 157 #define CONFIG_SYS_FSL_ESDHC_LE 158 #define CONFIG_SYS_FSL_IFC_LE 159 #define CONFIG_SYS_FSL_PEX_LUT_LE 160 161 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 162 163 /* SFP */ 164 #define CONFIG_SYS_FSL_SFP_VER_3_4 165 #define CONFIG_SYS_FSL_SFP_LE 166 #define CONFIG_SYS_FSL_SRK_LE 167 168 /* Security Monitor */ 169 #define CONFIG_SYS_FSL_SEC_MON_LE 170 171 /* Secure Boot */ 172 #define CONFIG_ESBC_HDR_LS 173 174 /* DCFG - GUR */ 175 #define CONFIG_SYS_FSL_CCSR_GUR_LE 176 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 177 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 178 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 179 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 180 181 /* LX2160A/LX2162A Soc Support */ 182 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 183 #define TZPC_BASE 0x02200000 184 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 185 #define SRDS_MAX_LANES 8 186 #ifndef L1_CACHE_BYTES 187 #define L1_CACHE_SHIFT 6 188 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 189 #endif 190 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 191 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } 192 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 193 194 #define CONFIG_SYS_PAGE_SIZE 0x10000 195 196 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 197 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 198 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 199 200 /* DDR */ 201 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 202 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 203 204 #define CONFIG_SYS_FSL_CCSR_GUR_LE 205 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 206 #define CONFIG_SYS_FSL_ESDHC_LE 207 #define CONFIG_SYS_FSL_PEX_LUT_LE 208 209 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 210 211 /* Generic Interrupt Controller Definitions */ 212 #define GICD_BASE 0x06000000 213 #define GICR_BASE 0x06200000 214 215 /* SMMU Definitions */ 216 #define SMMU_BASE 0x05000000 /* GR0 Base */ 217 218 /* SFP */ 219 #define CONFIG_SYS_FSL_SFP_VER_3_4 220 #define CONFIG_SYS_FSL_SFP_LE 221 #define CONFIG_SYS_FSL_SRK_LE 222 223 /* Security Monitor */ 224 #define CONFIG_SYS_FSL_SEC_MON_LE 225 226 /* Secure Boot */ 227 #define CONFIG_ESBC_HDR_LS 228 229 /* DCFG - GUR */ 230 #define CONFIG_SYS_FSL_CCSR_GUR_LE 231 232 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 233 234 #elif defined(CONFIG_ARCH_LS1028A) 235 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 236 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 237 #define CONFIG_FSL_TZPC_BP147 238 #define CONFIG_FSL_TZASC_400 239 240 /* TZ Protection Controller Definitions */ 241 #define TZPC_BASE 0x02200000 242 #define TZPCR0SIZE_BASE (TZPC_BASE) 243 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 244 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 245 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 246 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 247 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 248 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 249 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 250 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 251 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 252 253 #define SRDS_MAX_LANES 4 254 #define SRDS_BITS_PER_LANE 4 255 256 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 257 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ 258 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 259 260 /* Generic Interrupt Controller Definitions */ 261 #define GICD_BASE 0x06000000 262 #define GICR_BASE 0x06040000 263 264 /* SMMU Definitions */ 265 #define SMMU_BASE 0x05000000 /* GR0 Base */ 266 267 /* DDR */ 268 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 269 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 270 271 #define CONFIG_SYS_FSL_CCSR_GUR_LE 272 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 273 #define CONFIG_SYS_FSL_ESDHC_LE 274 #define CONFIG_SYS_FSL_PEX_LUT_LE 275 276 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 277 278 /* SFP */ 279 #define CONFIG_SYS_FSL_SFP_VER_3_4 280 #define CONFIG_SYS_FSL_SFP_LE 281 #define CONFIG_SYS_FSL_SRK_LE 282 283 /* SEC */ 284 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 285 286 /* Security Monitor */ 287 #define CONFIG_SYS_FSL_SEC_MON_LE 288 289 /* Secure Boot */ 290 #define CONFIG_ESBC_HDR_LS 291 292 /* DCFG - GUR */ 293 #define CONFIG_SYS_FSL_CCSR_GUR_LE 294 295 #elif defined(CONFIG_FSL_LSCH2) 296 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 297 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 298 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 299 300 #define DCSR_DCFG_SBEESR2 0x20140534 301 #define DCSR_DCFG_MBEESR2 0x20140544 302 303 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 304 #define CONFIG_SYS_FSL_ESDHC_BE 305 #define CONFIG_SYS_FSL_WDOG_BE 306 #define CONFIG_SYS_FSL_DSPI_BE 307 #define CONFIG_SYS_FSL_CCSR_GUR_BE 308 #define CONFIG_SYS_FSL_PEX_LUT_BE 309 310 /* SoC related */ 311 #ifdef CONFIG_ARCH_LS1043A 312 #define CONFIG_SYS_FMAN_V3 313 #define CONFIG_SYS_FSL_QMAN_V3 314 #define CONFIG_SYS_NUM_FMAN 1 315 #define CONFIG_SYS_NUM_FM1_DTSEC 7 316 #define CONFIG_SYS_NUM_FM1_10GEC 1 317 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 318 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 319 320 #define QE_MURAM_SIZE 0x6000UL 321 #define MAX_QE_RISC 1 322 #define QE_NUM_OF_SNUM 28 323 324 #define CONFIG_SYS_FSL_IFC_BE 325 #define CONFIG_SYS_FSL_SFP_VER_3_2 326 #define CONFIG_SYS_FSL_SEC_MON_BE 327 #define CONFIG_SYS_FSL_SFP_BE 328 #define CONFIG_SYS_FSL_SRK_LE 329 #define CONFIG_KEY_REVOCATION 330 331 /* SMMU Defintions */ 332 #define SMMU_BASE 0x09000000 333 334 /* Generic Interrupt Controller Definitions */ 335 #define GICD_BASE 0x01401000 336 #define GICC_BASE 0x01402000 337 #define GICH_BASE 0x01404000 338 #define GICV_BASE 0x01406000 339 #define GICD_SIZE 0x1000 340 #define GICC_SIZE 0x2000 341 #define GICH_SIZE 0x2000 342 #define GICV_SIZE 0x2000 343 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 344 #define GICD_BASE_64K 0x01410000 345 #define GICC_BASE_64K 0x01420000 346 #define GICH_BASE_64K 0x01440000 347 #define GICV_BASE_64K 0x01460000 348 #define GICD_SIZE_64K 0x10000 349 #define GICC_SIZE_64K 0x20000 350 #define GICH_SIZE_64K 0x20000 351 #define GICV_SIZE_64K 0x20000 352 #endif 353 354 #define DCFG_CCSR_SVR 0x1ee00a4 355 #define REV1_0 0x10 356 #define REV1_1 0x11 357 #define GIC_ADDR_BIT 31 358 #define SCFG_GIC400_ALIGN 0x1570188 359 360 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 361 362 #elif defined(CONFIG_ARCH_LS1012A) 363 #define GICD_BASE 0x01401000 364 #define GICC_BASE 0x01402000 365 #define CONFIG_SYS_FSL_SFP_VER_3_2 366 #define CONFIG_SYS_FSL_SEC_MON_BE 367 #define CONFIG_SYS_FSL_SFP_BE 368 #define CONFIG_SYS_FSL_SRK_LE 369 #define CONFIG_KEY_REVOCATION 370 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 371 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 372 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 373 374 #elif defined(CONFIG_ARCH_LS1046A) 375 #define CONFIG_SYS_FMAN_V3 376 #define CONFIG_SYS_FSL_QMAN_V3 377 #define CONFIG_SYS_NUM_FMAN 1 378 #define CONFIG_SYS_NUM_FM1_DTSEC 8 379 #define CONFIG_SYS_NUM_FM1_10GEC 2 380 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 381 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 382 383 #define CONFIG_SYS_FSL_IFC_BE 384 #define CONFIG_SYS_FSL_SFP_VER_3_2 385 #define CONFIG_SYS_FSL_SEC_MON_BE 386 #define CONFIG_SYS_FSL_SFP_BE 387 #define CONFIG_SYS_FSL_SRK_LE 388 #define CONFIG_KEY_REVOCATION 389 390 /* SMMU Defintions */ 391 #define SMMU_BASE 0x09000000 392 393 /* Generic Interrupt Controller Definitions */ 394 #define GICD_BASE 0x01410000 395 #define GICC_BASE 0x01420000 396 397 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 398 #else 399 #error SoC not defined 400 #endif 401 #endif 402 403 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 404