1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f0xx_ll_tim.h"
39 #include "stm32f0xx_ll_bus.h"
40
41 #ifdef USE_FULL_ASSERT
42 #include "stm32_assert.h"
43 #else
44 #define assert_param(expr) ((void)0U)
45 #endif
46
47 /** @addtogroup STM32F0xx_LL_Driver
48 * @{
49 */
50
51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
52
53 /** @addtogroup TIM_LL
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61 /** @addtogroup TIM_LL_Private_Macros
62 * @{
63 */
64 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
65 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
66 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
67 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
68 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
69
70 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
71 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
72 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
73
74 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
75 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
76 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
77 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
78 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
79 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
80 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
81 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
82
83 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
84 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
85
86 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
87 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
88
89 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
90 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
91
92 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
93 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
94 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
95
96 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
97 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
98 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
99 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
100
101 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
117
118 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
119 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
120 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
121
122 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
123 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
124 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
125
126 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
128
129 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
131
132 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
133 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
134
135 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
136 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
137 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
139
140 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
141 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
142
143 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
144 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
145
146 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
147 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
148 /**
149 * @}
150 */
151
152
153 /* Private function prototypes -----------------------------------------------*/
154 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
155 * @{
156 */
157 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
158 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
159 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
160 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
161 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
162 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
163 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
164 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
165 /**
166 * @}
167 */
168
169 /* Exported functions --------------------------------------------------------*/
170 /** @addtogroup TIM_LL_Exported_Functions
171 * @{
172 */
173
174 /** @addtogroup TIM_LL_EF_Init
175 * @{
176 */
177
178 /**
179 * @brief Set TIMx registers to their reset values.
180 * @param TIMx Timer instance
181 * @retval An ErrorStatus enumeration value:
182 * - SUCCESS: TIMx registers are de-initialized
183 * - ERROR: invalid TIMx instance
184 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)185 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
186 {
187 ErrorStatus result = SUCCESS;
188
189 /* Check the parameters */
190 assert_param(IS_TIM_INSTANCE(TIMx));
191
192 if (TIMx == TIM1)
193 {
194 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
195 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
196 }
197 #if defined (TIM2)
198 else if (TIMx == TIM2)
199 {
200 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
201 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
202 }
203 #endif
204 #if defined(TIM3)
205 else if (TIMx == TIM3)
206 {
207 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
208 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
209 }
210 #endif
211 #if defined(TIM5)
212 else if (TIMx == TIM5)
213 {
214 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
215 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
216 }
217 #endif
218 #if defined (TIM6)
219 else if (TIMx == TIM6)
220 {
221 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
222 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
223 }
224 #endif
225 #if defined (TIM7)
226 else if (TIMx == TIM7)
227 {
228 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
229 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
230 }
231 #endif
232 #if defined(TIM8)
233 else if (TIMx == TIM8)
234 {
235 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
236 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
237 }
238 #endif
239 #if defined (TIM14)
240 else if (TIMx == TIM14)
241 {
242 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
243 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
244 }
245 #endif
246 #if defined (TIM15)
247 else if (TIMx == TIM15)
248 {
249 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
250 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
251 }
252 #endif
253 #if defined (TIM16)
254 else if (TIMx == TIM16)
255 {
256 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
257 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
258 }
259 #endif
260 #if defined(TIM17)
261 else if (TIMx == TIM17)
262 {
263 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17);
264 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17);
265 }
266 #endif
267 else
268 {
269 result = ERROR;
270 }
271
272 return result;
273 }
274
275 /**
276 * @brief Set the fields of the time base unit configuration data structure
277 * to their default values.
278 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
279 * @retval None
280 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)281 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
282 {
283 /* Set the default configuration */
284 TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
285 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
286 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
287 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
288 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
289 }
290
291 /**
292 * @brief Configure the TIMx time base unit.
293 * @param TIMx Timer Instance
294 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
295 * @retval An ErrorStatus enumeration value:
296 * - SUCCESS: TIMx registers are de-initialized
297 * - ERROR: not applicable
298 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)299 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
300 {
301 uint32_t tmpcr1 = 0U;
302
303 /* Check the parameters */
304 assert_param(IS_TIM_INSTANCE(TIMx));
305 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
306 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
307
308 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
309
310 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
311 {
312 /* Select the Counter Mode */
313 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
314 }
315
316 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
317 {
318 /* Set the clock division */
319 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
320 }
321
322 /* Write to TIMx CR1 */
323 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
324
325 /* Set the Autoreload value */
326 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
327
328 /* Set the Prescaler value */
329 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
330
331 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
332 {
333 /* Set the Repetition Counter value */
334 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
335 }
336
337 /* Generate an update event to reload the Prescaler
338 and the repetition counter value (if applicable) immediately */
339 LL_TIM_GenerateEvent_UPDATE(TIMx);
340
341 return SUCCESS;
342 }
343
344 /**
345 * @brief Set the fields of the TIMx output channel configuration data
346 * structure to their default values.
347 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
348 * @retval None
349 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)350 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
351 {
352 /* Set the default configuration */
353 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
354 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
355 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
356 TIM_OC_InitStruct->CompareValue = 0x00000000U;
357 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
358 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
359 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
360 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
361 }
362
363 /**
364 * @brief Configure the TIMx output channel.
365 * @param TIMx Timer Instance
366 * @param Channel This parameter can be one of the following values:
367 * @arg @ref LL_TIM_CHANNEL_CH1
368 * @arg @ref LL_TIM_CHANNEL_CH2
369 * @arg @ref LL_TIM_CHANNEL_CH3
370 * @arg @ref LL_TIM_CHANNEL_CH4
371 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
372 * @retval An ErrorStatus enumeration value:
373 * - SUCCESS: TIMx output channel is initialized
374 * - ERROR: TIMx output channel is not initialized
375 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)376 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
377 {
378 ErrorStatus result = ERROR;
379
380 switch (Channel)
381 {
382 case LL_TIM_CHANNEL_CH1:
383 result = OC1Config(TIMx, TIM_OC_InitStruct);
384 break;
385 case LL_TIM_CHANNEL_CH2:
386 result = OC2Config(TIMx, TIM_OC_InitStruct);
387 break;
388 case LL_TIM_CHANNEL_CH3:
389 result = OC3Config(TIMx, TIM_OC_InitStruct);
390 break;
391 case LL_TIM_CHANNEL_CH4:
392 result = OC4Config(TIMx, TIM_OC_InitStruct);
393 break;
394 default:
395 break;
396 }
397
398 return result;
399 }
400
401 /**
402 * @brief Set the fields of the TIMx input channel configuration data
403 * structure to their default values.
404 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
405 * @retval None
406 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)407 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
408 {
409 /* Set the default configuration */
410 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
411 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
412 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
413 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
414 }
415
416 /**
417 * @brief Configure the TIMx input channel.
418 * @param TIMx Timer Instance
419 * @param Channel This parameter can be one of the following values:
420 * @arg @ref LL_TIM_CHANNEL_CH1
421 * @arg @ref LL_TIM_CHANNEL_CH2
422 * @arg @ref LL_TIM_CHANNEL_CH3
423 * @arg @ref LL_TIM_CHANNEL_CH4
424 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
425 * @retval An ErrorStatus enumeration value:
426 * - SUCCESS: TIMx output channel is initialized
427 * - ERROR: TIMx output channel is not initialized
428 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)429 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
430 {
431 ErrorStatus result = ERROR;
432
433 switch (Channel)
434 {
435 case LL_TIM_CHANNEL_CH1:
436 result = IC1Config(TIMx, TIM_IC_InitStruct);
437 break;
438 case LL_TIM_CHANNEL_CH2:
439 result = IC2Config(TIMx, TIM_IC_InitStruct);
440 break;
441 case LL_TIM_CHANNEL_CH3:
442 result = IC3Config(TIMx, TIM_IC_InitStruct);
443 break;
444 case LL_TIM_CHANNEL_CH4:
445 result = IC4Config(TIMx, TIM_IC_InitStruct);
446 break;
447 default:
448 break;
449 }
450
451 return result;
452 }
453
454 /**
455 * @brief Fills each TIM_EncoderInitStruct field with its default value
456 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
457 * @retval None
458 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)459 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
460 {
461 /* Set the default configuration */
462 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
463 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
464 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
465 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
466 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
467 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
468 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
469 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
470 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
471 }
472
473 /**
474 * @brief Configure the encoder interface of the timer instance.
475 * @param TIMx Timer Instance
476 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
477 * @retval An ErrorStatus enumeration value:
478 * - SUCCESS: TIMx registers are de-initialized
479 * - ERROR: not applicable
480 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)481 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
482 {
483 uint32_t tmpccmr1 = 0U;
484 uint32_t tmpccer = 0U;
485
486 /* Check the parameters */
487 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
488 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
489 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
490 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
491 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
492 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
493 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
494 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
495 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
496 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
497
498 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
499 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
500
501 /* Get the TIMx CCMR1 register value */
502 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
503
504 /* Get the TIMx CCER register value */
505 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
506
507 /* Configure TI1 */
508 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
509 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
510 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
511 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
512
513 /* Configure TI2 */
514 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
515 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
516 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
517 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
518
519 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
520 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
521 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
522 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
523 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
524
525 /* Set encoder mode */
526 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
527
528 /* Write to TIMx CCMR1 */
529 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
530
531 /* Write to TIMx CCER */
532 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
533
534 return SUCCESS;
535 }
536
537 /**
538 * @brief Set the fields of the TIMx Hall sensor interface configuration data
539 * structure to their default values.
540 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
541 * @retval None
542 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)543 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
544 {
545 /* Set the default configuration */
546 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
547 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
548 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
549 TIM_HallSensorInitStruct->CommutationDelay = 0U;
550 }
551
552 /**
553 * @brief Configure the Hall sensor interface of the timer instance.
554 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
555 * to the TI1 input channel
556 * @note TIMx slave mode controller is configured in reset mode.
557 Selected internal trigger is TI1F_ED.
558 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
559 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
560 * between 2 changes on the inputs. It gives information about motor speed.
561 * @note Channel 2 is configured in output PWM 2 mode.
562 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
563 * @note OC2REF is selected as trigger output on TRGO.
564 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
565 * when TIMx operates in Hall sensor interface mode.
566 * @param TIMx Timer Instance
567 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
568 * @retval An ErrorStatus enumeration value:
569 * - SUCCESS: TIMx registers are de-initialized
570 * - ERROR: not applicable
571 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)572 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
573 {
574 uint32_t tmpcr2 = 0U;
575 uint32_t tmpccmr1 = 0U;
576 uint32_t tmpccer = 0U;
577 uint32_t tmpsmcr = 0U;
578
579 /* Check the parameters */
580 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
581 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
582 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
583 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
584
585 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
586 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
587
588 /* Get the TIMx CR2 register value */
589 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
590
591 /* Get the TIMx CCMR1 register value */
592 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
593
594 /* Get the TIMx CCER register value */
595 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
596
597 /* Get the TIMx SMCR register value */
598 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
599
600 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
601 tmpcr2 |= TIM_CR2_TI1S;
602
603 /* OC2REF signal is used as trigger output (TRGO) */
604 tmpcr2 |= LL_TIM_TRGO_OC2REF;
605
606 /* Configure the slave mode controller */
607 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
608 tmpsmcr |= LL_TIM_TS_TI1F_ED;
609 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
610
611 /* Configure input channel 1 */
612 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
613 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
614 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
615 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
616
617 /* Configure input channel 2 */
618 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
619 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
620
621 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
622 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
623 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
624 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
625
626 /* Write to TIMx CR2 */
627 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
628
629 /* Write to TIMx SMCR */
630 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
631
632 /* Write to TIMx CCMR1 */
633 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
634
635 /* Write to TIMx CCER */
636 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
637
638 /* Write to TIMx CCR2 */
639 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
640
641 return SUCCESS;
642 }
643
644 /**
645 * @brief Set the fields of the Break and Dead Time configuration data structure
646 * to their default values.
647 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
648 * @retval None
649 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)650 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
651 {
652 /* Set the default configuration */
653 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
654 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
655 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
656 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
657 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
658 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
659 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
660 }
661
662 /**
663 * @brief Configure the Break and Dead Time feature of the timer instance.
664 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
665 * depending on the LOCK configuration, it can be necessary to configure all of
666 * them during the first write access to the TIMx_BDTR register.
667 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
668 * a timer instance provides a break input.
669 * @param TIMx Timer Instance
670 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
671 * @retval An ErrorStatus enumeration value:
672 * - SUCCESS: Break and Dead Time is initialized
673 * - ERROR: not applicable
674 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)675 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
676 {
677 uint32_t tmpbdtr = 0;
678
679 /* Check the parameters */
680 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
681 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
682 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
683 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
684 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
685 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
686 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
687
688 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
689 the OSSI State, the dead time value and the Automatic Output Enable Bit */
690
691 /* Set the BDTR bits */
692 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
693 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
694 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
695 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
696 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
697 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
698 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
699 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
700
701 /* Set TIMx_BDTR */
702 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
703
704 return SUCCESS;
705 }
706 /**
707 * @}
708 */
709
710 /**
711 * @}
712 */
713
714 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
715 * @brief Private functions
716 * @{
717 */
718 /**
719 * @brief Configure the TIMx output channel 1.
720 * @param TIMx Timer Instance
721 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
722 * @retval An ErrorStatus enumeration value:
723 * - SUCCESS: TIMx registers are de-initialized
724 * - ERROR: not applicable
725 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)726 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
727 {
728 uint32_t tmpccmr1 = 0U;
729 uint32_t tmpccer = 0U;
730 uint32_t tmpcr2 = 0U;
731
732 /* Check the parameters */
733 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
734 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
735 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
736 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
737 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
738 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
739
740 /* Disable the Channel 1: Reset the CC1E Bit */
741 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
742
743 /* Get the TIMx CCER register value */
744 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
745
746 /* Get the TIMx CR2 register value */
747 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
748
749 /* Get the TIMx CCMR1 register value */
750 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
751
752 /* Reset Capture/Compare selection Bits */
753 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
754
755 /* Set the Output Compare Mode */
756 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
757
758 /* Set the Output Compare Polarity */
759 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
760
761 /* Set the Output State */
762 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
763
764 if (IS_TIM_BREAK_INSTANCE(TIMx))
765 {
766 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
767 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
768
769 /* Set the complementary output Polarity */
770 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
771
772 /* Set the complementary output State */
773 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
774
775 /* Set the Output Idle state */
776 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
777
778 /* Set the complementary output Idle state */
779 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
780 }
781
782 /* Write to TIMx CR2 */
783 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
784
785 /* Write to TIMx CCMR1 */
786 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
787
788 /* Set the Capture Compare Register value */
789 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
790
791 /* Write to TIMx CCER */
792 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
793
794 return SUCCESS;
795 }
796
797 /**
798 * @brief Configure the TIMx output channel 2.
799 * @param TIMx Timer Instance
800 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
801 * @retval An ErrorStatus enumeration value:
802 * - SUCCESS: TIMx registers are de-initialized
803 * - ERROR: not applicable
804 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)805 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
806 {
807 uint32_t tmpccmr1 = 0U;
808 uint32_t tmpccer = 0U;
809 uint32_t tmpcr2 = 0U;
810
811 /* Check the parameters */
812 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
813 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
814 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
815 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
816 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
817 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
818
819 /* Disable the Channel 2: Reset the CC2E Bit */
820 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
821
822 /* Get the TIMx CCER register value */
823 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
824
825 /* Get the TIMx CR2 register value */
826 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
827
828 /* Get the TIMx CCMR1 register value */
829 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
830
831 /* Reset Capture/Compare selection Bits */
832 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
833
834 /* Select the Output Compare Mode */
835 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
836
837 /* Set the Output Compare Polarity */
838 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
839
840 /* Set the Output State */
841 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
842
843 if (IS_TIM_BREAK_INSTANCE(TIMx))
844 {
845 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
846 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
847
848 /* Set the complementary output Polarity */
849 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
850
851 /* Set the complementary output State */
852 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
853
854 /* Set the Output Idle state */
855 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
856
857 /* Set the complementary output Idle state */
858 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
859 }
860
861 /* Write to TIMx CR2 */
862 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
863
864 /* Write to TIMx CCMR1 */
865 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
866
867 /* Set the Capture Compare Register value */
868 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
869
870 /* Write to TIMx CCER */
871 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
872
873 return SUCCESS;
874 }
875
876 /**
877 * @brief Configure the TIMx output channel 3.
878 * @param TIMx Timer Instance
879 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
880 * @retval An ErrorStatus enumeration value:
881 * - SUCCESS: TIMx registers are de-initialized
882 * - ERROR: not applicable
883 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)884 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
885 {
886 uint32_t tmpccmr2 = 0U;
887 uint32_t tmpccer = 0U;
888 uint32_t tmpcr2 = 0U;
889
890 /* Check the parameters */
891 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
892 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
893 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
894 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
895 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
896 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
897
898 /* Disable the Channel 3: Reset the CC3E Bit */
899 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
900
901 /* Get the TIMx CCER register value */
902 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
903
904 /* Get the TIMx CR2 register value */
905 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
906
907 /* Get the TIMx CCMR2 register value */
908 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
909
910 /* Reset Capture/Compare selection Bits */
911 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
912
913 /* Select the Output Compare Mode */
914 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
915
916 /* Set the Output Compare Polarity */
917 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
918
919 /* Set the Output State */
920 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
921
922 if (IS_TIM_BREAK_INSTANCE(TIMx))
923 {
924 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
925 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
926
927 /* Set the complementary output Polarity */
928 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
929
930 /* Set the complementary output State */
931 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
932
933 /* Set the Output Idle state */
934 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
935
936 /* Set the complementary output Idle state */
937 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
938 }
939
940 /* Write to TIMx CR2 */
941 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
942
943 /* Write to TIMx CCMR2 */
944 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
945
946 /* Set the Capture Compare Register value */
947 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
948
949 /* Write to TIMx CCER */
950 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
951
952 return SUCCESS;
953 }
954
955 /**
956 * @brief Configure the TIMx output channel 4.
957 * @param TIMx Timer Instance
958 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
959 * @retval An ErrorStatus enumeration value:
960 * - SUCCESS: TIMx registers are de-initialized
961 * - ERROR: not applicable
962 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)963 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
964 {
965 uint32_t tmpccmr2 = 0U;
966 uint32_t tmpccer = 0U;
967 uint32_t tmpcr2 = 0U;
968
969 /* Check the parameters */
970 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
971 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
972 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
973 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
974 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
975 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
976
977 /* Disable the Channel 4: Reset the CC4E Bit */
978 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
979
980 /* Get the TIMx CCER register value */
981 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
982
983 /* Get the TIMx CR2 register value */
984 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
985
986 /* Get the TIMx CCMR2 register value */
987 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
988
989 /* Reset Capture/Compare selection Bits */
990 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
991
992 /* Select the Output Compare Mode */
993 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
994
995 /* Set the Output Compare Polarity */
996 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
997
998 /* Set the Output State */
999 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1000
1001 if (IS_TIM_BREAK_INSTANCE(TIMx))
1002 {
1003 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1004 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1005
1006 /* Set the Output Idle state */
1007 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1008 }
1009
1010 /* Write to TIMx CR2 */
1011 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1012
1013 /* Write to TIMx CCMR2 */
1014 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1015
1016 /* Set the Capture Compare Register value */
1017 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1018
1019 /* Write to TIMx CCER */
1020 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1021
1022 return SUCCESS;
1023 }
1024
1025
1026 /**
1027 * @brief Configure the TIMx input channel 1.
1028 * @param TIMx Timer Instance
1029 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1030 * @retval An ErrorStatus enumeration value:
1031 * - SUCCESS: TIMx registers are de-initialized
1032 * - ERROR: not applicable
1033 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1034 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1035 {
1036 /* Check the parameters */
1037 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1038 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1039 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1040 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1041 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1042
1043 /* Disable the Channel 1: Reset the CC1E Bit */
1044 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1045
1046 /* Select the Input and set the filter and the prescaler value */
1047 MODIFY_REG(TIMx->CCMR1,
1048 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1049 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1050
1051 /* Select the Polarity and set the CC1E Bit */
1052 MODIFY_REG(TIMx->CCER,
1053 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1054 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1055
1056 return SUCCESS;
1057 }
1058
1059 /**
1060 * @brief Configure the TIMx input channel 2.
1061 * @param TIMx Timer Instance
1062 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1063 * @retval An ErrorStatus enumeration value:
1064 * - SUCCESS: TIMx registers are de-initialized
1065 * - ERROR: not applicable
1066 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1067 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1068 {
1069 /* Check the parameters */
1070 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1071 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1072 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1073 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1074 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1075
1076 /* Disable the Channel 2: Reset the CC2E Bit */
1077 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1078
1079 /* Select the Input and set the filter and the prescaler value */
1080 MODIFY_REG(TIMx->CCMR1,
1081 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1082 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1083
1084 /* Select the Polarity and set the CC2E Bit */
1085 MODIFY_REG(TIMx->CCER,
1086 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1087 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1088
1089 return SUCCESS;
1090 }
1091
1092 /**
1093 * @brief Configure the TIMx input channel 3.
1094 * @param TIMx Timer Instance
1095 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1096 * @retval An ErrorStatus enumeration value:
1097 * - SUCCESS: TIMx registers are de-initialized
1098 * - ERROR: not applicable
1099 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1100 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1101 {
1102 /* Check the parameters */
1103 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1104 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1105 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1106 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1107 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1108
1109 /* Disable the Channel 3: Reset the CC3E Bit */
1110 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1111
1112 /* Select the Input and set the filter and the prescaler value */
1113 MODIFY_REG(TIMx->CCMR2,
1114 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1115 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1116
1117 /* Select the Polarity and set the CC3E Bit */
1118 MODIFY_REG(TIMx->CCER,
1119 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1120 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1121
1122 return SUCCESS;
1123 }
1124
1125 /**
1126 * @brief Configure the TIMx input channel 4.
1127 * @param TIMx Timer Instance
1128 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1129 * @retval An ErrorStatus enumeration value:
1130 * - SUCCESS: TIMx registers are de-initialized
1131 * - ERROR: not applicable
1132 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1133 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1134 {
1135 /* Check the parameters */
1136 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1137 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1138 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1139 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1140 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1141
1142 /* Disable the Channel 4: Reset the CC4E Bit */
1143 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1144
1145 /* Select the Input and set the filter and the prescaler value */
1146 MODIFY_REG(TIMx->CCMR2,
1147 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1148 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1149
1150 /* Select the Polarity and set the CC2E Bit */
1151 MODIFY_REG(TIMx->CCER,
1152 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1153 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1154
1155 return SUCCESS;
1156 }
1157
1158
1159 /**
1160 * @}
1161 */
1162
1163 /**
1164 * @}
1165 */
1166
1167 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1168
1169 /**
1170 * @}
1171 */
1172
1173 #endif /* USE_FULL_LL_DRIVER */
1174
1175 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1176