1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_qspi.h 4 * @author MCD Application Team 5 * @version V1.0.1 6 * @date 25-June-2015 7 * @brief Header file of QSPI HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32F7xx_HAL_QSPI_H 40 #define __STM32F7xx_HAL_QSPI_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32f7xx_hal_def.h" 48 49 /** @addtogroup STM32F7xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup QSPI 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup QSPI_Exported_Types QSPI Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief QSPI Init structure definition 64 */ 65 66 typedef struct { 67 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 68 This parameter can be a number between 0 and 255 */ 69 70 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 71 This parameter can be a value between 1 and 32 */ 72 73 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 74 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 75 This parameter can be a value of @ref QSPI_SampleShifting */ 76 77 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 78 required to address the flash memory. The flash capacity can be up to 4GB 79 (addressed using 32 bits) in indirect mode, but the addressable space in 80 memory-mapped mode is limited to 256MB 81 This parameter can be a number between 0 and 31 */ 82 83 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 84 of clock cycles which the chip select must remain high between commands. 85 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 86 87 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 88 This parameter can be a value of @ref QSPI_ClockMode */ 89 90 uint32_t FlashID; /* Specifies the Flash which will be used, 91 This parameter can be a value of @ref QSPI_Flash_Select */ 92 93 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 94 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 95 } QSPI_InitTypeDef; 96 97 /** 98 * @brief HAL QSPI State structures definition 99 */ 100 typedef enum { 101 HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ 102 HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ 103 HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ 104 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ 105 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ 106 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ 107 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ 108 HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ 109 } HAL_QSPI_StateTypeDef; 110 111 /** 112 * @brief QSPI Handle Structure definition 113 */ 114 typedef struct { 115 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 116 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 117 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 118 __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */ 119 __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */ 120 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 121 __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */ 122 __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */ 123 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 124 __IO HAL_LockTypeDef Lock; /* Locking object */ 125 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 126 __IO uint32_t ErrorCode; /* QSPI Error code */ 127 uint32_t Timeout; /* Timeout for the QSPI memory access */ 128 } QSPI_HandleTypeDef; 129 130 /** 131 * @brief QSPI Command structure definition 132 */ 133 typedef struct { 134 uint32_t Instruction; /* Specifies the Instruction to be sent 135 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 136 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 137 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 138 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 139 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 140 uint32_t AddressSize; /* Specifies the Address Size 141 This parameter can be a value of @ref QSPI_AddressSize */ 142 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 143 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 144 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 145 This parameter can be a number between 0 and 31 */ 146 uint32_t InstructionMode; /* Specifies the Instruction Mode 147 This parameter can be a value of @ref QSPI_InstructionMode */ 148 uint32_t AddressMode; /* Specifies the Address Mode 149 This parameter can be a value of @ref QSPI_AddressMode */ 150 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 151 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 152 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 153 This parameter can be a value of @ref QSPI_DataMode */ 154 uint32_t NbData; /* Specifies the number of data to transfer. 155 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 156 until end of memory)*/ 157 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 158 This parameter can be a value of @ref QSPI_DdrMode */ 159 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of 160 system clock in DDR mode. 161 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 162 uint32_t SIOOMode; /* Specifies the send instruction only once mode 163 This parameter can be a value of @ref QSPI_SIOOMode */ 164 } QSPI_CommandTypeDef; 165 166 /** 167 * @brief QSPI Auto Polling mode configuration structure definition 168 */ 169 typedef struct { 170 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 171 This parameter can be any value between 0 and 0xFFFFFFFF */ 172 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 173 This parameter can be any value between 0 and 0xFFFFFFFF */ 174 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 175 This parameter can be any value between 0 and 0xFFFF */ 176 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 177 This parameter can be any value between 1 and 4 */ 178 uint32_t MatchMode; /* Specifies the method used for determining a match. 179 This parameter can be a value of @ref QSPI_MatchMode */ 180 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 181 This parameter can be a value of @ref QSPI_AutomaticStop */ 182 } QSPI_AutoPollingTypeDef; 183 184 /** 185 * @brief QSPI Memory Mapped mode configuration structure definition 186 */ 187 typedef struct { 188 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 189 This parameter can be any value between 0 and 0xFFFF */ 190 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. 191 This parameter can be a value of @ref QSPI_TimeOutActivation */ 192 } QSPI_MemoryMappedTypeDef; 193 /** 194 * @} 195 */ 196 197 /* Exported constants --------------------------------------------------------*/ 198 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 199 * @{ 200 */ 201 /** @defgroup QSPI_ErrorCode QSPI Error Code 202 * @{ 203 */ 204 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ 205 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ 206 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ 207 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 213 * @{ 214 */ 215 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/ 216 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 217 /** 218 * @} 219 */ 220 221 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time 222 * @{ 223 */ 224 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/ 225 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 226 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 227 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 228 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 229 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 230 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 231 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 232 /** 233 * @} 234 */ 235 236 /** @defgroup QSPI_ClockMode QSPI Clock Mode 237 * @{ 238 */ 239 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/ 240 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 241 /** 242 * @} 243 */ 244 245 /** @defgroup QSPI_Flash_Select QSPI Flash Select 246 * @{ 247 */ 248 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) 249 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) 250 /** 251 * @} 252 */ 253 254 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 255 * @{ 256 */ 257 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) 258 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) 259 /** 260 * @} 261 */ 262 263 /** @defgroup QSPI_AddressSize QSPI Address Size 264 * @{ 265 */ 266 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/ 267 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 268 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 269 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 270 /** 271 * @} 272 */ 273 274 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 275 * @{ 276 */ 277 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/ 278 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 279 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 280 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 281 /** 282 * @} 283 */ 284 285 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 286 * @{ 287 */ 288 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/ 289 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 290 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 291 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 292 /** 293 * @} 294 */ 295 296 /** @defgroup QSPI_AddressMode QSPI Address Mode 297 * @{ 298 */ 299 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/ 300 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 301 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 302 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 303 /** 304 * @} 305 */ 306 307 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 308 * @{ 309 */ 310 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/ 311 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 312 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 313 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 314 /** 315 * @} 316 */ 317 318 /** @defgroup QSPI_DataMode QSPI Data Mode 319 * @{ 320 */ 321 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/ 322 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 323 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 324 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 325 /** 326 * @} 327 */ 328 329 /** @defgroup QSPI_DdrMode QSPI Ddr Mode 330 * @{ 331 */ 332 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/ 333 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 334 /** 335 * @} 336 */ 337 338 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle 339 * @{ 340 */ 341 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/ 342 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ 343 /** 344 * @} 345 */ 346 347 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode 348 * @{ 349 */ 350 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/ 351 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 352 /** 353 * @} 354 */ 355 356 /** @defgroup QSPI_MatchMode QSPI Match Mode 357 * @{ 358 */ 359 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/ 360 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 361 /** 362 * @} 363 */ 364 365 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 366 * @{ 367 */ 368 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/ 369 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 370 /** 371 * @} 372 */ 373 374 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation 375 * @{ 376 */ 377 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/ 378 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 379 /** 380 * @} 381 */ 382 383 /** @defgroup QSPI_Flags QSPI Flags 384 * @{ 385 */ 386 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 387 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 388 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 389 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 390 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 391 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 392 /** 393 * @} 394 */ 395 396 /** @defgroup QSPI_Interrupts QSPI Interrupts 397 * @{ 398 */ 399 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 400 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 401 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 402 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 403 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 404 /** 405 * @} 406 */ 407 408 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 409 * @{ 410 */ 411 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */ 412 /** 413 * @} 414 */ 415 416 /** 417 * @} 418 */ 419 420 /* Exported macros -----------------------------------------------------------*/ 421 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 422 * @{ 423 */ 424 425 /** @brief Reset QSPI handle state 426 * @param __HANDLE__: QSPI handle. 427 * @retval None 428 */ 429 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 430 431 /** @brief Enable QSPI 432 * @param __HANDLE__: specifies the QSPI Handle. 433 * @retval None 434 */ 435 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 436 437 /** @brief Disable QSPI 438 * @param __HANDLE__: specifies the QSPI Handle. 439 * @retval None 440 */ 441 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 442 443 /** @brief Enables the specified QSPI interrupt. 444 * @param __HANDLE__: specifies the QSPI Handle. 445 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. 446 * This parameter can be one of the following values: 447 * @arg QSPI_IT_TO: QSPI Time out interrupt 448 * @arg QSPI_IT_SM: QSPI Status match interrupt 449 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 450 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 451 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 452 * @retval None 453 */ 454 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 455 456 457 /** @brief Disables the specified QSPI interrupt. 458 * @param __HANDLE__: specifies the QSPI Handle. 459 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. 460 * This parameter can be one of the following values: 461 * @arg QSPI_IT_TO: QSPI Timeout interrupt 462 * @arg QSPI_IT_SM: QSPI Status match interrupt 463 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 464 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 465 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 466 * @retval None 467 */ 468 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 469 470 /** @brief Checks whether the specified QSPI interrupt source is enabled. 471 * @param __HANDLE__: specifies the QSPI Handle. 472 * @param __INTERRUPT__: specifies the QSPI interrupt source to check. 473 * This parameter can be one of the following values: 474 * @arg QSPI_IT_TO: QSPI Time out interrupt 475 * @arg QSPI_IT_SM: QSPI Status match interrupt 476 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 477 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 478 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 479 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 480 */ 481 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 482 483 /** 484 * @brief Get the selected QSPI's flag status. 485 * @param __HANDLE__: specifies the QSPI Handle. 486 * @param __FLAG__: specifies the QSPI flag to check. 487 * This parameter can be one of the following values: 488 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 489 * @arg QSPI_FLAG_TO: QSPI Time out flag 490 * @arg QSPI_FLAG_SM: QSPI Status match flag 491 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 492 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 493 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 494 * @retval None 495 */ 496 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) 497 498 /** @brief Clears the specified QSPI's flag status. 499 * @param __HANDLE__: specifies the QSPI Handle. 500 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set 501 * This parameter can be one of the following values: 502 * @arg QSPI_FLAG_TO: QSPI Time out flag 503 * @arg QSPI_FLAG_SM: QSPI Status match flag 504 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 505 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 506 * @retval None 507 */ 508 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 509 /** 510 * @} 511 */ 512 513 /* Exported functions --------------------------------------------------------*/ 514 /** @addtogroup QSPI_Exported_Functions 515 * @{ 516 */ 517 518 /** @addtogroup QSPI_Exported_Functions_Group1 519 * @{ 520 */ 521 /* Initialization/de-initialization functions ********************************/ 522 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 523 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 524 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 525 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 526 /** 527 * @} 528 */ 529 530 /** @addtogroup QSPI_Exported_Functions_Group2 531 * @{ 532 */ 533 /* IO operation functions *****************************************************/ 534 /* QSPI IRQ handler method */ 535 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 536 537 /* QSPI indirect mode */ 538 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, const QSPI_CommandTypeDef *cmd, uint32_t Timeout); 539 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 540 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 541 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, const QSPI_CommandTypeDef *cmd); 542 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 543 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 544 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 545 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 546 547 /* QSPI status flag polling mode */ 548 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, const QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 549 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, const QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 550 551 /* QSPI memory-mapped mode */ 552 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, const QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 553 /** 554 * @} 555 */ 556 557 /** @addtogroup QSPI_Exported_Functions_Group3 558 * @{ 559 */ 560 /* Callback functions in non-blocking modes ***********************************/ 561 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 562 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 563 564 /* QSPI indirect mode */ 565 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 566 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 567 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 568 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 569 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 570 571 /* QSPI status flag polling mode */ 572 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 573 574 /* QSPI memory-mapped mode */ 575 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 576 /** 577 * @} 578 */ 579 580 /** @addtogroup QSPI_Exported_Functions_Group4 581 * @{ 582 */ 583 /* Peripheral Control and State functions ************************************/ 584 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi); 585 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi); 586 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 587 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 588 /** 589 * @} 590 */ 591 592 /** 593 * @} 594 */ 595 596 /* Private types -------------------------------------------------------------*/ 597 /* Private variables ---------------------------------------------------------*/ 598 /* Private constants ---------------------------------------------------------*/ 599 /** @defgroup QSPI_Private_Constants QSPI Private Constants 600 * @{ 601 */ 602 603 /** 604 * @} 605 */ 606 607 /* Private macros ------------------------------------------------------------*/ 608 /** @defgroup QSPI_Private_Macros QSPI Private Macros 609 * @{ 610 */ 611 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler 612 * @{ 613 */ 614 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) 615 /** 616 * @} 617 */ 618 619 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold 620 * @{ 621 */ 622 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32)) 623 /** 624 * @} 625 */ 626 627 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 628 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 629 630 /** @defgroup QSPI_FlashSize QSPI Flash Size 631 * @{ 632 */ 633 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) 634 /** 635 * @} 636 */ 637 638 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 639 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 640 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 641 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 642 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 643 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 644 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 645 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 646 647 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 648 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 649 650 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ 651 ((FLA) == QSPI_FLASH_ID_2)) 652 653 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 654 ((MODE) == QSPI_DUALFLASH_DISABLE)) 655 656 657 /** @defgroup QSPI_Instruction QSPI Instruction 658 * @{ 659 */ 660 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) 661 /** 662 * @} 663 */ 664 665 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 666 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 667 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 668 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 669 670 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 671 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 672 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 673 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 674 675 676 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles 677 * @{ 678 */ 679 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) 680 /** 681 * @} 682 */ 683 684 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 685 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 686 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 687 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 688 689 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 690 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 691 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 692 ((MODE) == QSPI_ADDRESS_4_LINES)) 693 694 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 695 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 696 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 697 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 698 699 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 700 ((MODE) == QSPI_DATA_1_LINE) || \ 701 ((MODE) == QSPI_DATA_2_LINES) || \ 702 ((MODE) == QSPI_DATA_4_LINES)) 703 704 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 705 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 706 707 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 708 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 709 710 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 711 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 712 713 /** @defgroup QSPI_Interval QSPI Interval 714 * @{ 715 */ 716 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 717 /** 718 * @} 719 */ 720 721 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size 722 * @{ 723 */ 724 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) 725 /** 726 * @} 727 */ 728 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 729 ((MODE) == QSPI_MATCH_MODE_OR)) 730 731 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 732 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 733 734 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 735 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 736 737 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period 738 * @{ 739 */ 740 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) 741 /** 742 * @} 743 */ 744 745 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ 746 ((FLAG) == QSPI_FLAG_TO) || \ 747 ((FLAG) == QSPI_FLAG_SM) || \ 748 ((FLAG) == QSPI_FLAG_FT) || \ 749 ((FLAG) == QSPI_FLAG_TC) || \ 750 ((FLAG) == QSPI_FLAG_TE)) 751 752 #define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000)) 753 /** 754 * @} 755 */ 756 757 /* Private functions ---------------------------------------------------------*/ 758 /** @defgroup QSPI_Private_Functions QSPI Private Functions 759 * @{ 760 */ 761 762 /** 763 * @} 764 */ 765 766 /** 767 * @} 768 */ 769 770 /** 771 * @} 772 */ 773 774 #ifdef __cplusplus 775 } 776 #endif 777 778 #endif /* __STM32F7xx_HAL_QSPI_H */ 779 780 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 781