1 /* 2 * Copyright (c) 2019-2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_V1_H 8 #define NEOVERSE_V1_H 9 10 #define NEOVERSE_V1_MIDR U(0x410FD400) 11 12 /* Neoverse V1 loop count for CVE-2022-23960 mitigation */ 13 #define NEOVERSE_V1_BHB_LOOP_COUNT U(32) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 20 #define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 21 #define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 22 #define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 23 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 24 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 25 #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) 26 #define CPUECTLR_EL1_PF_MODE_LSB U(6) 27 #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) 28 29 /******************************************************************************* 30 * CPU Power Control register specific definitions 31 ******************************************************************************/ 32 #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 33 #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 34 35 /******************************************************************************* 36 * CPU Auxiliary Control register specific definitions. 37 ******************************************************************************/ 38 #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 39 #define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) 40 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 41 #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) 42 #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) 43 44 #endif /* NEOVERSE_V1_H */ 45