1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef PPU_V1_H
9 #define PPU_V1_H
10 
11 /*!
12  * \cond
13  */
14 
15 #include <mod_ppu_v1.h>
16 #include <mod_timer.h>
17 
18 #include <fwk_macros.h>
19 
20 #include <stdbool.h>
21 #include <stdint.h>
22 
23 /*
24  * PPU 1.1 register definitions
25  */
26 struct ppu_v1_reg {
27   FWK_RW  uint32_t PWPR;
28   FWK_RW  uint32_t PMER;
29   FWK_R   uint32_t PWSR;
30           uint32_t RESERVED0;
31   FWK_R   uint32_t DISR;
32   FWK_R   uint32_t MISR;
33   FWK_R   uint32_t STSR;
34   FWK_RW  uint32_t UNLK;
35   FWK_RW  uint32_t PWCR;
36   FWK_RW  uint32_t PTCR;
37           uint32_t RESERVED1[2];
38   FWK_RW  uint32_t IMR;
39   FWK_RW  uint32_t AIMR;
40   FWK_RW  uint32_t ISR;
41   FWK_RW  uint32_t AISR;
42   FWK_RW  uint32_t IESR;
43   FWK_RW  uint32_t OPSR;
44           uint32_t RESERVED2[2];
45   FWK_RW  uint32_t FUNRR;
46   FWK_RW  uint32_t FULRR;
47   FWK_RW  uint32_t MEMRR;
48           uint8_t  RESERVED3[0x160 - 0x5C];
49   FWK_RW  uint32_t EDTR0;
50   FWK_RW  uint32_t EDTR1;
51           uint32_t RESERVED4[2];
52   FWK_RW  uint32_t DCCR0;
53   FWK_RW  uint32_t DCCR1;
54           uint8_t  RESERVED5[0xFB0 - 0x178];
55   FWK_R   uint32_t IDR0;
56   FWK_R   uint32_t IDR1;
57           uint8_t  RESERVED6[0xFC8 - 0xFB8];
58   FWK_R   uint32_t IIDR;
59   FWK_R   uint32_t AIDR;
60           uint8_t  RESERVED7[0x1000 - 0xFD0];
61 };
62 
63 enum ppu_v1_mode {
64     PPU_V1_MODE_OFF         = 0,
65     PPU_V1_MODE_OFF_EMU     = 1,
66     PPU_V1_MODE_MEM_RET     = 2,
67     PPU_V1_MODE_MEM_RET_EMU = 3,
68     PPU_V1_MODE_LOGIC_RET   = 4,
69     PPU_V1_MODE_FULL_RET    = 5,
70     PPU_V1_MODE_MEM_OFF     = 6,
71     PPU_V1_MODE_FUNC_RET    = 7,
72     PPU_V1_MODE_ON          = 8,
73     PPU_V1_MODE_WARM_RST    = 9,
74     PPU_V1_MODE_DBG_RECOV   = 10,
75     /* No valid modes after this line */
76     PPU_V1_MODE_COUNT
77 };
78 
79 enum ppu_v1_op_devactive {
80     PPU_V1_OP_DEVACTIVE_0,
81     PPU_V1_OP_DEVACTIVE_1,
82     PPU_V1_OP_DEVACTIVE_2,
83     PPU_V1_OP_DEVACTIVE_3,
84     PPU_V1_OP_DEVACTIVE_INDEPENDENT_COUNT,
85     PPU_V1_OP_DEVACTIVE_4 = 4,
86     PPU_V1_OP_DEVACTIVE_5,
87     PPU_V1_OP_DEVACTIVE_6,
88     PPU_V1_OP_DEVACTIVE_7,
89     /* No valid operating mode devactive signal number after this line */
90     PPU_V1_OP_DEVACTIVE_COUNT
91 };
92 
93 /*
94  * Bit definitions for PWPR
95  */
96 #define PPU_V1_PWPR_PWR_POLICY_POS   0
97 #define PPU_V1_PWPR_OP_POLICY_POS    16
98 
99 #define PPU_V1_PWPR_POLICY       UINT32_C(0x0000000F)
100 #define PPU_V1_PWPR_DYNAMIC_EN   UINT32_C(0x00000100)
101 #define PPU_V1_PWPR_OFF_LOCK_EN  UINT32_C(0x00001000)
102 #define PPU_V1_PWPR_OP_POLICY    UINT32_C(0x000F0000)
103 #define PPU_V1_PWPR_OP_DYN_EN    UINT32_C(0x01000000)
104 
105 /*
106  * Bit definitions for PWSR
107  */
108 #define PPU_V1_PWSR_PWR_STATUS_POS   0
109 #define PPU_V1_PWSR_OP_STATUS_POS    16
110 
111 #define PPU_V1_PWSR_PWR_STATUS       UINT32_C(0x0000000F)
112 #define PPU_V1_PWSR_PWR_DYN_STATUS   UINT32_C(0x00000100)
113 #define PPU_V1_PWSR_OFF_LOCK_STATUS  UINT32_C(0x00001000)
114 #define PPU_V1_PWSR_OP_STATUS        UINT32_C(0x000F0000)
115 #define PPU_V1_PWSR_OP_DYN_STATUS    UINT32_C(0x01000000)
116 
117 /*
118  * Bit definitions for DISR
119  */
120 #define PPU_V1_DISR_PWR_DEVACTIVE_STATUS_POS 0
121 #define PPU_V1_DISR_OP_DEVACTIVE_STATUS_POS 24
122 
123 /*
124  * Bit definitions for UNLK
125  */
126 #define PPU_V1_UNLK_OFF_UNLOCK       UINT32_C(0x00000001)
127 
128 /*
129  * Bit definitions for PWCR
130  */
131 #define PPU_V1_PWCR_DEV_REQ_EN        UINT32_C(0x000000FF)
132 #define PPU_V1_PWCR_DEV_ACTIVE_EN     UINT32_C(0x0007FF00)
133 #define PPU_V1_PWCR_OP_DEV_ACTIVE_EN  UINT32_C(0xFF000000)
134 
135 /*
136  * Definitions for IESR and OPSR
137  */
138 enum ppu_v1_edge_sensitivity {
139     PPU_V1_EDGE_SENSITIVITY_MASKED,
140     PPU_V1_EDGE_SENSITIVITY_RISING_EDGE,
141     PPU_V1_EDGE_SENSITIVITY_FALLING_EDGE,
142     PPU_V1_EDGE_SENSITIVITY_BOTH_EDGES,
143     /* No valid edge sensitivity after this line */
144     PPU_V1_EDGE_SENSITIVITY_COUNT
145 };
146 
147 #define PPU_V1_BITS_PER_EDGE_SENSITIVITY 2
148 #define PPU_V1_EDGE_SENSITIVITY_MASK  0x3
149 
150 /*
151  * Bit definitions for IMR
152  */
153 #define PPU_V1_IMR_MASK                     UINT32_C(0x0000003F)
154 #define PPU_V1_IMR_STA_POLICY_TRN_IRQ_MASK  UINT32_C(0x00000001)
155 #define PPU_V1_IMR_STA_ACCEPT_IRQ_MASK      UINT32_C(0x00000002)
156 #define PPU_V1_IMR_STA_DENY_IRQ_MASK        UINT32_C(0x00000004)
157 #define PPU_V1_IMR_EMU_ACCEPT_IRQ_MASK      UINT32_C(0x00000008)
158 #define PPU_V1_IMR_EMU_DENY_IRQ_MASK        UINT32_C(0x00000010)
159 #define PPU_V1_IMR_DYN_POLICY_MIN_IRQ_MASK  UINT32_C(0x00000020)
160 
161 /*
162  * Bit definitions for AIMR
163  */
164 #define PPU_V1_AIMR_MASK                     UINT32_C(0x0000001F)
165 #define PPU_V1_AIMR_UNSPT_POLICY_IRQ_MASK    UINT32_C(0x00000001)
166 #define PPU_V1_AIMR_DYN_ACCEPT_IRQ_MASK      UINT32_C(0x00000002)
167 #define PPU_V1_AIMR_DYN_DENY_IRQ_MASK        UINT32_C(0x00000004)
168 #define PPU_V1_AIMR_STA_POLICY_PWR_IRQ_MASK  UINT32_C(0x00000008)
169 #define PPU_V1_AIMR_STA_POLICY_OP_IRQ_MASK   UINT32_C(0x00000010)
170 
171 /*
172  * Bit definitions for ISR
173  */
174 #define PPU_V1_ISR_MASK                        UINT32_C(0xFF07FFBF)
175 #define PPU_V1_ISR_STA_POLICY_TRN_IRQ          UINT32_C(0x00000001)
176 #define PPU_V1_ISR_STA_ACCEPT_IRQ              UINT32_C(0x00000002)
177 #define PPU_V1_ISR_STA_DENY_IRQ                UINT32_C(0x00000004)
178 #define PPU_V1_ISR_EMU_ACCEPT_IRQ              UINT32_C(0x00000008)
179 #define PPU_V1_ISR_EMU_DENY_IRQ                UINT32_C(0x00000010)
180 #define PPU_V1_ISR_DYN_POLICY_MIN_IRQ          UINT32_C(0x00000020)
181 #define PPU_V1_ISR_OTHER_IRQ                   UINT32_C(0x00000080)
182 #define PPU_V1_ISR_ACTIVE_EDGE_POS             8
183 #define PPU_V1_ISR_ACTIVE_EDGE_IRQ_MASK        UINT32_C(0x0007FF00)
184 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE0_IRQ     UINT32_C(0x00000100)
185 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE1_IRQ     UINT32_C(0x00000200)
186 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE2_IRQ     UINT32_C(0x00000400)
187 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE3_IRQ     UINT32_C(0x00000800)
188 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE4_IRQ     UINT32_C(0x00001000)
189 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE5_IRQ     UINT32_C(0x00002000)
190 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE6_IRQ     UINT32_C(0x00004000)
191 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE7_IRQ     UINT32_C(0x00008000)
192 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE8_IRQ     UINT32_C(0x00010000)
193 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE9_IRQ     UINT32_C(0x00020000)
194 #define PPU_V1_ISR_ACTIVE_EDGE_ACTIVE10_IRQ    UINT32_C(0x00040000)
195 #define PPU_V1_ISR_OP_ACTIVE_EDGE_POS          24
196 #define PPU_V1_ISR_OP_ACTIVE_EDGE_IRQ_MASK     UINT32_C(0xFF000000)
197 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE0_IRQ  UINT32_C(0x01000000)
198 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE1_IRQ  UINT32_C(0x02000000)
199 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE2_IRQ  UINT32_C(0x04000000)
200 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE3_IRQ  UINT32_C(0x08000000)
201 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE4_IRQ  UINT32_C(0x10000000)
202 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE5_IRQ  UINT32_C(0x20000000)
203 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE6_IRQ  UINT32_C(0x40000000)
204 #define PPU_V1_ISR_OP_ACTIVE_EDGE_ACTIVE7_IRQ  UINT32_C(0x80000000)
205 
206 /*
207  * Bit definitions for AISR
208  */
209 #define PPU_V1_AISR_MASK                UINT32_C(0x0000001F)
210 #define PPU_V1_AISR_UNSPT_POLICY_IRQ    UINT32_C(0x00000001)
211 #define PPU_V1_AISR_DYN_ACCEPT_IRQ      UINT32_C(0x00000002)
212 #define PPU_V1_AISR_DYN_DENY_IRQ        UINT32_C(0x00000004)
213 #define PPU_V1_AISR_STA_POLICY_PWR_IRQ  UINT32_C(0x00000008)
214 #define PPU_V1_AISR_STA_POLICY_OP_IRQ   UINT32_C(0x00000010)
215 
216 /*
217  * Bit definitions for AIDR
218  */
219 #define PPU_V1_AIDR_ARCH_REV_MINOR  UINT32_C(0x0000000F)
220 #define PPU_V1_AIDR_ARCH_REV_MAJOR  UINT32_C(0x000000F0)
221 
222 /*
223  * Definitions for PPU Arch version ID
224  */
225 #define PPU_V1_ARCH_ID  0x11
226 
227 /*
228  * Bit definitions for IDR0
229  */
230 #define PPU_V1_IDR0_NUM_OPMODE_POS    4
231 #define PPU_V1_IDR0_NUM_OPMODE        UINT32_C(0x000000F0)
232 
233 /*
234  * Timer context to be passed to set_power_mode function.
235  */
236 struct ppu_v1_timer_ctx {
237     fwk_id_t timer_id;
238     struct mod_timer_api *timer_api;
239     uint32_t delay_us;
240 };
241 
242 /*
243  * Initializes the PPU by masking all interrupts and acknowledging any
244  * previously pending interrupt.
245  */
246 void ppu_v1_init(struct ppu_v1_reg *ppu);
247 
248 /*
249  * Set PPU's power mode and wait for the transition.
250  * Note: This function currently supports only synchronous transitions with
251  *       limited error detection.
252  */
253 int ppu_v1_set_power_mode(
254     struct ppu_v1_reg *ppu,
255     enum ppu_v1_mode ppu_mode,
256     struct ppu_v1_timer_ctx *timer_ctx);
257 
258 /*
259  * Request PPU's power mode and don't wait for the transition.
260  */
261 int ppu_v1_request_power_mode(struct ppu_v1_reg *ppu,
262                               enum ppu_v1_mode ppu_mode);
263 
264 /*
265  * Request a change to the PPU's operating mode.
266  */
267 int ppu_v1_request_operating_mode(struct ppu_v1_reg *ppu,
268                                   enum ppu_v1_opmode op_mode);
269 
270 /*
271  * Enable PPU's dynamic operating mode transitions
272  */
273 void ppu_v1_opmode_dynamic_enable(struct ppu_v1_reg *ppu,
274                                   enum ppu_v1_opmode min_dyn_mode);
275 
276 /*
277  * Enable PPU's dynamic power mode transitions
278  */
279 void ppu_v1_dynamic_enable(struct ppu_v1_reg *ppu,
280                            enum ppu_v1_mode min_dyn_state);
281 
282 /*
283  * Enable the lock in the OFF state
284  */
285 void ppu_v1_lock_off_enable(struct ppu_v1_reg *ppu);
286 
287 /*
288  * Disable the lock in the OFF state
289  */
290 void ppu_v1_lock_off_disable(struct ppu_v1_reg *ppu);
291 
292 /*
293  * Get the current power mode.
294  */
295 enum ppu_v1_mode ppu_v1_get_power_mode(struct ppu_v1_reg *ppu);
296 
297 /*
298  * Get the current programmed power policy mode.
299  */
300 enum ppu_v1_mode ppu_v1_get_programmed_power_mode(struct ppu_v1_reg *ppu);
301 
302 /*
303  * Get the current operating mode.
304  */
305 enum ppu_v1_opmode ppu_v1_get_operating_mode(struct ppu_v1_reg *ppu);
306 
307 /*
308  * Get the current programmed operating mode policy.
309  */
310 enum ppu_v1_opmode ppu_v1_get_programmed_operating_mode(struct ppu_v1_reg *ppu);
311 
312 /*
313  * Check whether the dynamic transitions are enabled or not.
314  */
315 bool ppu_v1_is_dynamic_enabled(struct ppu_v1_reg *ppu);
316 
317 /*
318  * Check whether the locked in the MEM_RET or OFF state.
319  */
320 bool ppu_v1_is_locked(struct ppu_v1_reg *ppu);
321 
322 /*
323  * Check if the DEVACTIVE signal associated to a power mode is high.
324  */
325 bool ppu_v1_is_power_devactive_high(struct ppu_v1_reg *ppu,
326                                     enum ppu_v1_mode ppu_mode);
327 
328 /*
329  * Check if the DEVACTIVE signal associated to an operating mode is high.
330  */
331 bool ppu_v1_is_op_devactive_high(struct ppu_v1_reg *ppu,
332                                  enum ppu_v1_op_devactive op_devactive);
333 
334 /*
335  * Unlock the power domain from the OFF power mode.
336  */
337 void ppu_v1_off_unlock(struct ppu_v1_reg *ppu);
338 
339 /*
340  * Disable the check of the DEVACTIVE signals by the PPU logic for state
341  * transition.
342  */
343 void ppu_v1_disable_devactive(struct ppu_v1_reg *ppu);
344 
345 /*
346  * Disable the handshake with the P-channel or the Q-channels
347  */
348 void ppu_v1_disable_handshake(struct ppu_v1_reg *ppu);
349 
350 /*
351  * Set one or more bits of the interrupt mask register.
352  */
353 void ppu_v1_interrupt_mask(struct ppu_v1_reg *ppu, unsigned int mask);
354 
355 /*
356  * Set one or more bits of the additional interrupt mask register.
357  */
358 void ppu_v1_additional_interrupt_mask(struct ppu_v1_reg *ppu,
359     unsigned int mask);
360 
361 /*
362  * Clear one or more bits of the interrupt mask register.
363  */
364 void ppu_v1_interrupt_unmask(struct ppu_v1_reg *ppu, unsigned int mask);
365 
366 /*
367  * Clear one or more bits of the additional interrupt mask register.
368  */
369 void ppu_v1_additional_interrupt_unmask(struct ppu_v1_reg *ppu,
370     unsigned int mask);
371 
372 /*
373  * Check if some additional interrupts are pending.
374  */
375 bool ppu_v1_is_additional_interrupt_pending(struct ppu_v1_reg *ppu,
376     unsigned int mask);
377 
378 /*
379  * Acknowledge one or more interrupts.
380  */
381 void ppu_v1_ack_interrupt(struct ppu_v1_reg *ppu, unsigned int mask);
382 
383 /*
384  * Acknowledge one or more additional interrupts.
385  */
386 void ppu_v1_ack_additional_interrupt(struct ppu_v1_reg *ppu, unsigned int mask);
387 
388 /*
389  * Set input edge sensitivity. See 'enum ppu_v1_edge_sensitivity' for the
390  * available sensitivities.
391  */
392 void ppu_v1_set_input_edge_sensitivity(struct ppu_v1_reg *ppu,
393     enum ppu_v1_mode ppu_mode, enum ppu_v1_edge_sensitivity edge_sensitivity);
394 
395 /*
396  * Get input edge sensitivity. See 'enum ppu_v1_edge_sensitivity' for the
397  * available sensitivities.
398  */
399 enum ppu_v1_edge_sensitivity ppu_v1_get_input_edge_sensitivity(
400     struct ppu_v1_reg *ppu, enum ppu_v1_mode ppu_mode);
401 
402 /*
403  * Acknowledge a power active edge interrupt.
404  */
405 void ppu_v1_ack_power_active_edge_interrupt(struct ppu_v1_reg *ppu,
406                                             enum ppu_v1_mode ppu_mode);
407 
408 /*
409  * Check if a power active edge interrupt is pending.
410  */
411 bool ppu_v1_is_power_active_edge_interrupt(struct ppu_v1_reg *ppu,
412                                            enum ppu_v1_mode ppu_mode);
413 
414 /*
415  * Set operating mode active edge sensitivity. See
416  * 'enum ppu_v1_edge_sensitivity' for the available sensitivities.
417  */
418 void ppu_v1_set_op_active_edge_sensitivity(struct ppu_v1_reg *ppu,
419     enum ppu_v1_op_devactive op_devactive,
420     enum ppu_v1_edge_sensitivity edge_sensitivity);
421 
422 /*
423  * Get operating mode active edge sensitivity.
424  * See 'enum ppu_v1_edge_sensitivity for the available sensitivities.
425  */
426 enum ppu_v1_edge_sensitivity ppu_v1_get_op_active_edge_sensitivity(
427     struct ppu_v1_reg *ppu, enum ppu_v1_op_devactive op_devactive);
428 
429 /*
430  * Acknowledge operating mode active edge interrupt.
431  */
432 void ppu_v1_ack_op_active_edge_interrupt(struct ppu_v1_reg *ppu,
433     enum ppu_v1_op_devactive op_devactive);
434 
435 /*
436  * Check if an operating mode active edge interrupt is pending.
437  */
438 bool ppu_v1_is_op_active_edge_interrupt(struct ppu_v1_reg *ppu,
439     enum ppu_v1_op_devactive op_devactive);
440 
441 /*
442  * Check if the DYN input edge interrupt is pending.
443  */
444 bool ppu_v1_is_dyn_policy_min_interrupt(struct ppu_v1_reg *ppu);
445 
446 /*
447  * Get the number of operating modes.
448  */
449 unsigned int ppu_v1_get_num_opmode(struct ppu_v1_reg *ppu);
450 
451 /*
452  * Get the PPU architecture ID.
453  */
454 unsigned int ppu_v1_get_arch_id(struct ppu_v1_reg *ppu);
455 
456 /*!
457  * \endcond
458  */
459 
460 #endif  /* PPU_V1_H */
461